8077c3a0901242c0177c922af57d80ed22c8a919
[openwrt/staging/blocktrron.git] / target / linux / ipq806x / files-6.1 / arch / arm / boot / dts / qcom-ipq8064-d7800.dts
1 #include "qcom-ipq8064-v2.0-smb208.dtsi"
2
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/leds/common.h>
5
6 / {
7 model = "Netgear Nighthawk X4 D7800";
8 compatible = "netgear,d7800", "qcom,ipq8064";
9
10 memory@0 {
11 reg = <0x42000000 0x1e000000>;
12 device_type = "memory";
13 };
14
15 reserved-memory {
16 rsvd@5fe00000 {
17 reg = <0x5fe00000 0x200000>;
18 reusable;
19 };
20 };
21
22 aliases {
23 mdio-gpio0 = &mdio0;
24
25 led-boot = &power_white;
26 led-failsafe = &power_amber;
27 led-running = &power_white;
28 led-upgrade = &power_amber;
29 };
30
31 chosen {
32 bootargs = "rootfstype=squashfs noinitrd";
33 };
34
35 keys {
36 compatible = "gpio-keys";
37 pinctrl-0 = <&button_pins>;
38 pinctrl-names = "default";
39
40 wifi {
41 label = "wifi";
42 gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_RFKILL>;
44 debounce-interval = <60>;
45 wakeup-source;
46 };
47
48 reset {
49 label = "reset";
50 gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
51 linux,code = <KEY_RESTART>;
52 debounce-interval = <60>;
53 wakeup-source;
54 };
55
56 wps {
57 label = "wps";
58 gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
59 linux,code = <KEY_WPS_BUTTON>;
60 debounce-interval = <60>;
61 wakeup-source;
62 };
63 };
64
65 leds {
66 compatible = "gpio-leds";
67 pinctrl-0 = <&led_pins>;
68 pinctrl-names = "default";
69
70 usb1 {
71 label = "white:usb1";
72 gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
73 };
74
75 usb2 {
76 label = "white:usb2";
77 gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
78 };
79
80 power_amber: power_amber {
81 function = LED_FUNCTION_POWER;
82 color = <LED_COLOR_ID_AMBER>;
83 gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
84 };
85
86 wan_white {
87 function = LED_FUNCTION_WAN;
88 color = <LED_COLOR_ID_WHITE>;
89 gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
90 };
91
92 wan_amber {
93 function = LED_FUNCTION_WAN;
94 color = <LED_COLOR_ID_AMBER>;
95 gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
96 };
97
98 wps {
99 function = LED_FUNCTION_WPS;
100 color = <LED_COLOR_ID_WHITE>;
101 gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
102 };
103
104 esata {
105 label = "white:esata";
106 gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
107 };
108
109 power_white: power_white {
110 function = LED_FUNCTION_POWER;
111 color = <LED_COLOR_ID_WHITE>;
112 gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
113 default-state = "keep";
114 };
115
116 wifi {
117 label = "white:wifi";
118 gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
119 };
120 };
121 };
122
123 &qcom_pinmux {
124 button_pins: button_pins {
125 mux {
126 pins = "gpio6", "gpio54", "gpio65";
127 function = "gpio";
128 drive-strength = <2>;
129 bias-pull-up;
130 };
131 };
132
133 led_pins: led_pins {
134 mux {
135 pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
136 "gpio24","gpio26", "gpio53", "gpio64";
137 function = "gpio";
138 drive-strength = <2>;
139 bias-pull-up;
140 };
141 };
142
143 usb0_pwr_en_pins: usb0_pwr_en_pins {
144 mux {
145 pins = "gpio15";
146 function = "gpio";
147 drive-strength = <12>;
148 bias-pull-down;
149 output-high;
150 };
151 };
152
153 usb1_pwr_en_pins: usb1_pwr_en_pins {
154 mux {
155 pins = "gpio16", "gpio68";
156 function = "gpio";
157 drive-strength = <12>;
158 bias-pull-down;
159 output-high;
160 };
161 };
162 };
163
164 &sata_phy {
165 status = "okay";
166 };
167
168 &sata {
169 status = "okay";
170 };
171
172 &hs_phy_0 {
173 status = "okay";
174 };
175
176 &ss_phy_0 {
177 status = "okay";
178 };
179
180 &usb3_0 {
181 status = "okay";
182
183 pinctrl-0 = <&usb0_pwr_en_pins>;
184 pinctrl-names = "default";
185 };
186
187 &hs_phy_1 {
188 status = "okay";
189 };
190
191 &ss_phy_1 {
192 status = "okay";
193 };
194
195 &usb3_1 {
196 status = "okay";
197
198 pinctrl-0 = <&usb1_pwr_en_pins>;
199 pinctrl-names = "default";
200 };
201
202 &pcie0 {
203 status = "okay";
204 reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
205 pinctrl-0 = <&pcie0_pins>;
206 pinctrl-names = "default";
207
208 bridge@0,0 {
209 reg = <0x00000000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 ranges;
213
214 wifi@1,0 {
215 compatible = "pci168c,0040";
216 reg = <0x00010000 0 0 0 0>;
217
218 nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
219 nvmem-cell-names = "mac-address", "pre-calibration";
220 };
221 };
222 };
223
224 &pcie1 {
225 status = "okay";
226 reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
227 pinctrl-0 = <&pcie1_pins>;
228 pinctrl-names = "default";
229 max-link-speed = <1>;
230
231 bridge@0,0 {
232 reg = <0x00000000 0 0 0 0>;
233 #address-cells = <3>;
234 #size-cells = <2>;
235 ranges;
236
237 wifi@1,0 {
238 compatible = "pci168c,0040";
239 reg = <0x00010000 0 0 0 0>;
240
241 nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
242 nvmem-cell-names = "mac-address", "pre-calibration";
243 };
244 };
245 };
246
247 &pcie2 {
248 status = "okay";
249 reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
250 pinctrl-0 = <&pcie2_pins>;
251 pinctrl-names = "default";
252 };
253
254 &nand {
255 status = "okay";
256
257 nand@0 {
258 reg = <0>;
259 compatible = "qcom,nandcs";
260
261 nand-ecc-strength = <4>;
262 nand-bus-width = <8>;
263 nand-ecc-step-size = <512>;
264
265 nand-is-boot-medium;
266 qcom,boot-partitions = <0x0 0x1180000>;
267
268 partitions {
269 compatible = "fixed-partitions";
270 #address-cells = <1>;
271 #size-cells = <1>;
272
273 qcadata@0 {
274 label = "qcadata";
275 reg = <0x0000000 0x0c80000>;
276 read-only;
277 };
278
279 APPSBL@c80000 {
280 label = "APPSBL";
281 reg = <0x0c80000 0x0500000>;
282 read-only;
283 };
284
285 APPSBLENV@1180000 {
286 label = "APPSBLENV";
287 reg = <0x1180000 0x0080000>;
288 read-only;
289 };
290
291 art@1200000 {
292 label = "art";
293 reg = <0x1200000 0x0140000>;
294 read-only;
295
296 nvmem-layout {
297 compatible = "fixed-layout";
298 #address-cells = <1>;
299 #size-cells = <1>;
300
301 macaddr_art_0: macaddr@0 {
302 reg = <0x0 0x6>;
303 };
304
305 macaddr_art_6: macaddr@6 {
306 compatible = "mac-base";
307 reg = <0x6 0x6>;
308 #nvmem-cell-cells = <1>;
309 };
310
311 precal_art_1000: precal@1000 {
312 reg = <0x1000 0x2f20>;
313 };
314
315 precal_art_5000: precal@5000 {
316 reg = <0x5000 0x2f20>;
317 };
318 };
319 };
320
321 artbak: art@1340000 {
322 label = "artbak";
323 reg = <0x1340000 0x0140000>;
324 read-only;
325 };
326
327 kernel@1480000 {
328 label = "kernel";
329 reg = <0x1480000 0x0400000>;
330 };
331
332 ubi@1880000 {
333 label = "ubi";
334 reg = <0x1880000 0x6080000>;
335 };
336
337 reserve@7900000 {
338 label = "reserve";
339 reg = <0x7900000 0x0700000>;
340 read-only;
341 };
342 };
343 };
344 };
345
346 &mdio0 {
347 status = "okay";
348
349 pinctrl-0 = <&mdio0_pins>;
350 pinctrl-names = "default";
351
352 switch@10 {
353 compatible = "qca,qca8337";
354 #address-cells = <1>;
355 #size-cells = <0>;
356 reg = <0x10>;
357
358 ports {
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 port@0 {
363 reg = <0>;
364 label = "cpu";
365 ethernet = <&gmac1>;
366 phy-mode = "rgmii";
367 tx-internal-delay-ps = <1000>;
368 rx-internal-delay-ps = <1000>;
369
370 fixed-link {
371 speed = <1000>;
372 full-duplex;
373 };
374 };
375
376 port@1 {
377 reg = <1>;
378 label = "lan1";
379 phy-mode = "internal";
380 phy-handle = <&phy_port1>;
381 };
382
383 port@2 {
384 reg = <2>;
385 label = "lan2";
386 phy-mode = "internal";
387 phy-handle = <&phy_port2>;
388 };
389
390 port@3 {
391 reg = <3>;
392 label = "lan3";
393 phy-mode = "internal";
394 phy-handle = <&phy_port3>;
395 };
396
397 port@4 {
398 reg = <4>;
399 label = "lan4";
400 phy-mode = "internal";
401 phy-handle = <&phy_port4>;
402 };
403
404 port@5 {
405 reg = <5>;
406 label = "wan";
407 phy-mode = "internal";
408 phy-handle = <&phy_port5>;
409 };
410
411 port@6 {
412 reg = <6>;
413 label = "cpu";
414 ethernet = <&gmac2>;
415 phy-mode = "sgmii";
416 qca,sgmii-enable-pll;
417
418 fixed-link {
419 speed = <1000>;
420 full-duplex;
421 };
422 };
423 };
424
425 mdio {
426 #address-cells = <1>;
427 #size-cells = <0>;
428
429 phy_port1: phy@0 {
430 reg = <0>;
431 };
432
433 phy_port2: phy@1 {
434 reg = <1>;
435 };
436
437 phy_port3: phy@2 {
438 reg = <2>;
439 };
440
441 phy_port4: phy@3 {
442 reg = <3>;
443 };
444
445 phy_port5: phy@4 {
446 reg = <4>;
447 };
448 };
449 };
450 };
451
452 &gmac1 {
453 status = "okay";
454 phy-mode = "rgmii";
455 qcom,id = <1>;
456
457 pinctrl-0 = <&rgmii2_pins>;
458 pinctrl-names = "default";
459
460 nvmem-cells = <&macaddr_art_6 0>;
461 nvmem-cell-names = "mac-address";
462
463 fixed-link {
464 speed = <1000>;
465 full-duplex;
466 };
467 };
468
469 &gmac2 {
470 status = "okay";
471 phy-mode = "sgmii";
472 qcom,id = <2>;
473
474 nvmem-cells = <&macaddr_art_0>;
475 nvmem-cell-names = "mac-address";
476
477 fixed-link {
478 speed = <1000>;
479 full-duplex;
480 };
481 };
482
483 &adm_dma {
484 status = "okay";
485 };