target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-r619ac.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         chosen {
  11                 bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
  12         };
  13
  14         aliases {
  15                 led-boot = &led_sys;
  16                 led-failsafe = &led_sys;
  17                 led-running = &led_sys;
  18                 led-upgrade = &led_sys;
  19         };
  20
  21         soc {
  22                 rng@22000 {
  23                         status = "okay";
  24                 };
  25
  26                 mdio@90000 {
  27                         status = "okay";
  28                         pinctrl-0 = <&mdio_pins>;
  29                         pinctrl-names = "default";
  30                 };
  31
  32                 tcsr@1949000 {
  33                         compatible = "qcom,tcsr";
  34                         reg = <0x1949000 0x100>;
  35                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  36                 };
  37
  38                 tcsr@194b000 {
  39                         compatible = "qcom,tcsr";
  40                         reg = <0x194b000 0x100>;
  41                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  42                 };
  43
  44                 ess_tcsr@1953000 {
  45                         compatible = "qcom,tcsr";
  46                         reg = <0x1953000 0x1000>;
  47                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  48                 };
  49
  50                 tcsr@1957000 {
  51                         compatible = "qcom,tcsr";
  52                         reg = <0x1957000 0x100>;
  53                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  54                 };
  55
  56                 usb2@60f8800 {
  57                         status = "okay";
  58                 };
  59
  60                 usb3@8af8800 {
  61                         status = "okay";
  62                 };
  63
  64                 crypto@8e3a000 {
  65                         status = "okay";
  66                 };
  67
  68                 watchdog@b017000 {
  69                         status = "okay";
  70                 };
  71         };
  72
  73         leds {
  74                 compatible = "gpio-leds";
  75
  76                 led_sys: led-0 {
  77                         label = "blue:sys";
  78                         gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
  79                         color = <LED_COLOR_ID_BLUE>;
  80                         function = LED_FUNCTION_POWER;
  81                 };
  82
  83                 led-1 {
  84                         label = "blue:wlan2g";
  85                         gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
  86                         linux,default-trigger = "phy0tpt";
  87                         color = <LED_COLOR_ID_BLUE>;
  88                         function = LED_FUNCTION_WLAN;
  89                         function-enumerator = <0>;
  90                 };
  91
  92                 led-2 {
  93                         label = "blue:wlan5g";
  94                         gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
  95                         linux,default-trigger = "phy1tpt";
  96                         color = <LED_COLOR_ID_BLUE>;
  97                         function = LED_FUNCTION_WLAN;
  98                         function-enumerator = <1>;
  99                 };
 100         };
 101
 102         keys {
 103                 compatible = "gpio-keys";
 104
 105                 reset {
 106                         label = "reset";
 107                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
 108                         linux,code = <KEY_RESTART>;
 109                 };
 110         };
 111 };
 112
 113 &blsp_dma {
 114         status = "okay";
 115 };
 116
 117 &blsp1_spi1 {
 118         status = "okay";
 119
 120         flash@0 {
 121                 reg = <0>;
 122                 compatible = "jedec,spi-nor";
 123                 spi-max-frequency = <24000000>;
 124
 125                 partitions {
 126                         compatible = "fixed-partitions";
 127                         #address-cells = <1>;
 128                         #size-cells = <1>;
 129
 130                         partition@0 {
 131                                 label = "SBL1";
 132                                 reg = <0x0 0x40000>;
 133                                 read-only;
 134                         };
 135
 136                         partition@40000 {
 137                                 label = "MIBIB";
 138                                 reg = <0x40000 0x20000>;
 139                                 read-only;
 140                         };
 141
 142                         partition@60000 {
 143                                 label = "QSEE";
 144                                 reg = <0x60000 0x60000>;
 145                                 read-only;
 146                         };
 147
 148                         partition@c0000 {
 149                                 label = "CDT";
 150                                 reg = <0xc0000 0x10000>;
 151                                 read-only;
 152                         };
 153
 154                         partition@d0000 {
 155                                 label = "DDRPARAMS";
 156                                 reg = <0xd0000 0x10000>;
 157                                 read-only;
 158                         };
 159
 160                         partition@e0000 {
 161                                 label = "APPSBLENV";
 162                                 reg = <0xe0000 0x10000>;
 163                                 read-only;
 164                         };
 165
 166                         partition@f0000 {
 167                                 label = "APPSBL";
 168                                 reg = <0xf0000 0x80000>;
 169                                 read-only;
 170                         };
 171
 172                         partition@170000 {
 173                                 label = "ART";
 174                                 reg = <0x170000 0x10000>;
 175                                 read-only;
 176
 177                                 nvmem-layout {
 178                                         compatible = "fixed-layout";
 179                                         #address-cells = <1>;
 180                                         #size-cells = <1>;
 181
 182                                         precal_art_1000: precal@1000 {
 183                                                 reg = <0x1000 0x2f20>;
 184                                         };
 185
 186                                         precal_art_5000: precal@5000 {
 187                                                 reg = <0x5000 0x2f20>;
 188                                         };
 189                                 };
 190                         };
 191                 };
 192         };
 193 };
 194
 195 &nand {
 196         status = "okay";
 197
 198         nand@0 {
 199                 partitions {
 200                         compatible = "fixed-partitions";
 201                         #address-cells = <1>;
 202                         #size-cells = <1>;
 203
 204                         nand_rootfs: partition@0 {
 205                                 label = "ubi";
 206                                 /* reg defined in 64M/128M variant dts. */
 207                         };
 208                 };
 209         };
 210 };
 211
 212 &blsp1_uart1 {
 213         pinctrl-0 = <&serial_0_pins>;
 214         pinctrl-names = "default";
 215         status = "okay";
 216 };
 217
 218 &cryptobam {
 219         status = "okay";
 220 };
 221
 222 &pcie0 {
 223         status = "okay";
 224         pinctrl-names = "default";
 225         pinctrl-0 = <&pcie_pins>;
 226         perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
 227         wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
 228
 229         /* Free slot for use */
 230         bridge@0,0 {
 231                 reg = <0x00000000 0 0 0 0>;
 232                 #address-cells = <3>;
 233                 #size-cells = <2>;
 234                 ranges;
 235         };
 236 };
 237
 238 &qpic_bam {
 239         status = "okay";
 240 };
 241
 242 &sdhci {
 243         pinctrl-0 = <&sd_0_pins>;
 244         pinctrl-names = "default";
 245         vqmmc-supply = <&vqmmc>;
 246         status = "okay";
 247 };
 248
 249 &tlmm {
 250         pcie_pins: pcie_pinmux {
 251                 mux {
 252                         pins = "gpio2";
 253                         function = "gpio";
 254                         output-low;
 255                         bias-pull-down;
 256                 };
 257         };
 258
 259         mdio_pins: mdio_pinmux {
 260                 mux_1 {
 261                         pins = "gpio6";
 262                         function = "mdio";
 263                         bias-pull-up;
 264                 };
 265
 266                 mux_2 {
 267                         pins = "gpio7";
 268                         function = "mdc";
 269                         bias-pull-up;
 270                 };
 271         };
 272
 273         sd_0_pins: sd_0_pinmux {
 274                 mux_1 {
 275                         pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
 276                         function = "sdio";
 277                         drive-strength = <10>;
 278                 };
 279
 280                 mux_2 {
 281                         pins = "gpio27";
 282                         function = "sdio";
 283                         drive-strength = <16>;
 284                 };
 285         };
 286
 287         serial_0_pins: serial0-pinmux {
 288                 mux {
 289                         pins = "gpio16", "gpio17";
 290                         function = "blsp_uart0";
 291                         bias-disable;
 292                 };
 293         };
 294 };
 295
 296 &ethphy0 {
 297         qcom,single-led-1000;
 298         qcom,single-led-100;
 299         qcom,single-led-10;
 300 };
 301
 302 &ethphy1 {
 303         qcom,single-led-1000;
 304         qcom,single-led-100;
 305         qcom,single-led-10;
 306 };
 307
 308 &ethphy2 {
 309         qcom,single-led-1000;
 310         qcom,single-led-100;
 311         qcom,single-led-10;
 312 };
 313
 314 &ethphy3 {
 315         qcom,single-led-1000;
 316         qcom,single-led-100;
 317         qcom,single-led-10;
 318 };
 319
 320 &ethphy4 {
 321         qcom,single-led-1000;
 322         qcom,single-led-100;
 323         qcom,single-led-10;
 324 };
 325
 326 &gmac {
 327         status = "okay";
 328 };
 329
 330 &switch {
 331         status = "okay";
 332 };
 333
 334 &swport1 {
 335         status = "okay";
 336
 337         label = "lan4";
 338 };
 339
 340 &swport2 {
 341         status = "okay";
 342
 343         label = "lan3";
 344 };
 345
 346 &swport3 {
 347         status = "okay";
 348
 349         label = "lan2";
 350 };
 351
 352 &swport4 {
 353         status = "okay";
 354
 355         label = "lan1";
 356 };
 357
 358 &swport5 {
 359         status = "okay";
 360 };
 361
 362 &usb3_ss_phy {
 363         status = "okay";
 364 };
 365
 366 &usb3_hs_phy {
 367         status = "okay";
 368 };
 369
 370 &usb2_hs_phy {
 371         status = "okay";
 372 };
 373
 374 &vqmmc {
 375         status = "okay";
 376 };
 377
 378 &wifi0 {
 379         status = "okay";
 380         nvmem-cell-names = "pre-calibration";
 381         nvmem-cells = <&precal_art_1000>;
 382         qcom,ath10k-calibration-variant = "P&W-R619AC";
 383 };
 384
 385 &wifi1 {
 386         status = "okay";
 387         nvmem-cell-names = "pre-calibration";
 388         nvmem-cells = <&precal_art_5000>;
 389         qcom,ath10k-calibration-variant = "P&W-R619AC";
 390 };