dc144a15847cbf1b0fdacca34a2b26c6bd731d2a
[openwrt/staging/hauke.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4019-eap2200.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 / {
8 model = "EnGenius EAP2200";
9 compatible = "engenius,eap2200";
10
11 aliases {
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
16 };
17
18 keys {
19 compatible = "gpio-keys";
20
21 wps {
22 label = "wps";
23 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
24 linux,code = <KEY_WPS_BUTTON>;
25 };
26 };
27
28 leds {
29 compatible = "gpio-leds";
30
31 led_power: power {
32 label = "amber:power";
33 gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
34 };
35
36 lan1 {
37 label = "blue:lan1";
38 gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
39 };
40
41 lan2 {
42 label = "blue:lan2";
43 gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
44 };
45
46 wlan2g {
47 label = "blue:wlan2g";
48 gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
49 linux,default-trigger = "phy0tpt";
50 };
51
52 wlan5g {
53 label = "yellow:wlan5g";
54 gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
55 linux,default-trigger = "phy1tpt";
56 };
57
58 wlan5g2 {
59 label = "yellow:wlan5g2";
60 gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
61 linux,default-trigger = "phy2tpt";
62 };
63
64 mode {
65 label = "blue:mode";
66 gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
67 };
68 };
69
70 soc {
71 rng@22000 {
72 status = "okay";
73 };
74
75 mdio@90000 {
76 status = "okay";
77 };
78
79 crypto@8e3a000 {
80 status = "okay";
81 };
82
83 watchdog@b017000 {
84 status = "okay";
85 };
86 };
87 };
88
89 &blsp_dma {
90 status = "okay";
91 };
92
93 &blsp1_spi1 {
94 pinctrl-0 = <&spi_0_pins>;
95 pinctrl-names = "default";
96 status = "okay";
97 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
98
99 flash@0 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "jedec,spi-nor";
103 reg = <0>;
104 spi-max-frequency = <24000000>;
105 partitions {
106 compatible = "fixed-partitions";
107 #address-cells = <1>;
108 #size-cells = <1>;
109
110 partition0@0 {
111 label = "0:SBL1";
112 reg = <0x00000000 0x00040000>;
113 read-only;
114 };
115 partition1@40000 {
116 label = "0:MIBIB";
117 reg = <0x00040000 0x00020000>;
118 read-only;
119 };
120 partition2@60000 {
121 label = "0:QSEE";
122 reg = <0x00060000 0x00060000>;
123 read-only;
124 };
125 partition3@c0000 {
126 label = "0:CDT";
127 reg = <0x000c0000 0x00010000>;
128 read-only;
129 };
130 partition4@d0000 {
131 label = "0:DDRPARAMS";
132 reg = <0x000d0000 0x00010000>;
133 read-only;
134 };
135 partition5@e0000 {
136 label = "0:APPSBLENV";
137 reg = <0x000e0000 0x00010000>;
138 read-only;
139 };
140 partition6@f0000 {
141 label = "0:APPSBL";
142 reg = <0x000f0000 0x00080000>;
143 read-only;
144 };
145 partition7@170000 {
146 label = "0:ART";
147 reg = <0x00170000 0x00010000>;
148 read-only;
149 compatible = "nvmem-cells";
150 #address-cells = <1>;
151 #size-cells = <1>;
152
153 precal_art_1000: precal@1000 {
154 reg = <0x1000 0x2f20>;
155 };
156
157 precal_art_5000: precal@5000 {
158 reg = <0x5000 0x2f20>;
159 };
160
161 precal_art_9000: precal@9000 {
162 reg = <0x9000 0x2f20>;
163 };
164 };
165 };
166 };
167 };
168
169 &blsp1_uart1 {
170 pinctrl-0 = <&serial_0_pins>;
171 pinctrl-names = "default";
172 status = "okay";
173 };
174
175 &cryptobam {
176 status = "okay";
177 };
178
179 &nand {
180 pinctrl-0 = <&nand_pins>;
181 pinctrl-names = "default";
182 status = "okay";
183
184 nand@0 {
185 partitions {
186 compatible = "fixed-partitions";
187 #address-cells = <1>;
188 #size-cells = <1>;
189
190 partition@0 {
191 label = "rootfs1";
192 reg = <0x00000000 0x04000000>;
193 };
194 partition@40000000 {
195 label = "ubi";
196 reg = <0x04000000 0x04000000>;
197 };
198
199 };
200 };
201 };
202
203 &pcie0 {
204 status = "okay";
205 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
206 wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
207
208 bridge@0,0 {
209 reg = <0x00000000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 ranges;
213
214 wifi2: wifi@1,0 {
215 compatible = "qcom,ath10k";
216 reg = <0x00010000 0 0 0 0>;
217 nvmem-cell-names = "pre-calibration";
218 nvmem-cells = <&precal_art_9000>;
219 ieee80211-freq-limit = <5470000 5875000>;
220 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
221 };
222 };
223 };
224
225 &qpic_bam {
226 status = "okay";
227 };
228
229 &tlmm {
230 nand_pins: nand_pins {
231 pullups {
232 pins = "gpio53", "gpio58", "gpio59";
233 function = "qpic";
234 bias-pull-up;
235 };
236
237 pulldowns {
238 pins = "gpio54", "gpio55", "gpio56",
239 "gpio57", "gpio60", "gpio61",
240 "gpio62", "gpio63", "gpio64",
241 "gpio65", "gpio66", "gpio67",
242 "gpio68", "gpio69";
243 function = "qpic";
244 bias-pull-down;
245 };
246 };
247
248 serial_0_pins: serial_pinmux {
249 mux {
250 pins = "gpio16", "gpio17";
251 function = "blsp_uart0";
252 bias-disable;
253 };
254 };
255
256 spi_0_pins: spi_0_pinmux {
257 pinmux {
258 function = "blsp_spi0";
259 pins = "gpio13", "gpio14", "gpio15";
260 drive-strength = <12>;
261 bias-disable;
262 };
263 pinmux_cs {
264 function = "gpio";
265 pins = "gpio12";
266 drive-strength = <2>;
267 bias-disable;
268 output-high;
269 };
270 };
271 };
272
273 &wifi0 {
274 status = "okay";
275 nvmem-cell-names = "pre-calibration";
276 nvmem-cells = <&precal_art_1000>;
277 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
278 };
279
280 &wifi1 {
281 status = "okay";
282 ieee80211-freq-limit = <5170000 5350000>;
283 nvmem-cell-names = "pre-calibration";
284 nvmem-cells = <&precal_art_5000>;
285 qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
286 };