target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi

   1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
   2  * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  */
  17
  18 #include "qcom-ipq4019.dtsi"
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/input/input.h>
  21 #include <dt-bindings/soc/qcom,tcsr.h>
  22
  23 / {
  24         model = "Netgear EX61X0v2";
  25         compatible = "netgear,ex61x0v2";
  26
  27         soc {
  28                 rng@22000 {
  29                         status = "okay";
  30                 };
  31
  32                 mdio@90000 {
  33                         status = "okay";
  34                 };
  35
  36                 tcsr@1949000 {
  37                         compatible = "qcom,tcsr";
  38                         reg = <0x1949000 0x100>;
  39                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  40                 };
  41
  42                 ess_tcsr@1953000 {
  43                         compatible = "qcom,tcsr";
  44                         reg = <0x1953000 0x1000>;
  45                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  46                 };
  47
  48                 tcsr@1957000 {
  49                         compatible = "qcom,tcsr";
  50                         reg = <0x1957000 0x100>;
  51                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  52                 };
  53
  54                 crypto@8e3a000 {
  55                         status = "okay";
  56                 };
  57
  58                 watchdog@b017000 {
  59                         status = "okay";
  60                 };
  61         };
  62
  63         aliases {
  64                 led-boot = &power_amber;
  65                 led-failsafe = &power_amber;
  66                 led-running = &power_green;
  67                 led-upgrade = &power_amber;
  68                 label-mac-device = &gmac;
  69         };
  70
  71         keys {
  72                 compatible = "gpio-keys";
  73
  74                 wps {
  75                         label = "wps";
  76                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  77                         linux,code = <KEY_WPS_BUTTON>;
  78                 };
  79
  80                 reset {
  81                         label = "reset";
  82                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  83                         linux,code = <KEY_RESTART>;
  84                 };
  85         };
  86
  87         led_spi {
  88                 compatible = "spi-gpio";
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91
  92                 sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  93                 mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  94                 num-chipselects = <0>;
  95
  96                 led_gpio: led_gpio@0 {
  97                         compatible = "fairchild,74hc595";
  98                         reg = <0>;
  99                         gpio-controller;
 100                         #gpio-cells = <2>;
 101                         registers-number = <1>;
 102                         spi-max-frequency = <1000000>;
 103                 };
 104         };
 105
 106         leds {
 107                 compatible = "gpio-leds";
 108
 109                 power_amber: power_amber {
 110                         label = "amber:power";
 111                         gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 112                 };
 113
 114                 power_green: power_green {
 115                         label = "green:power";
 116                         gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 117                 };
 118
 119                 right {
 120                         label = "blue:right";
 121                         gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 122                 };
 123
 124                 left {
 125                         label = "blue:left";
 126                         gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 127                 };
 128
 129                 client_green {
 130                         label = "green:client";
 131                         gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 132                 };
 133
 134                 client_red {
 135                         label = "red:client";
 136                         gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 137                 };
 138
 139                 router_green {
 140                         label = "green:router";
 141                         gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
 142                 };
 143
 144                 router_red {
 145                         label = "red:router";
 146                         gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 147                 };
 148
 149                 wps {
 150                         label = "green:wps";
 151                         gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 152                 };
 153         };
 154 };
 155
 156 &tlmm {
 157         serial_pins: serial_pinmux {
 158                 mux {
 159                         pins = "gpio60", "gpio61";
 160                         function = "blsp_uart0";
 161                         bias-disable;
 162                 };
 163         };
 164
 165         spi_0_pins: spi_0_pinmux {
 166                 pin {
 167                         function = "blsp_spi0";
 168                         pins = "gpio55", "gpio56", "gpio57";
 169                         drive-strength = <12>;
 170                         bias-disable;
 171                 };
 172                 pin_cs {
 173                         function = "gpio";
 174                         pins = "gpio54";
 175                         drive-strength = <2>;
 176                         bias-disable;
 177                         output-high;
 178                 };
 179         };
 180 };
 181
 182 &blsp1_spi1 {
 183         pinctrl-0 = <&spi_0_pins>;
 184         pinctrl-names = "default";
 185         status = "okay";
 186         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 187
 188         mx25l12805d@0 {
 189                 compatible = "jedec,spi-nor";
 190                 reg = <0>;
 191                 spi-max-frequency = <45000000>;
 192
 193                 partitions {
 194                         compatible = "fixed-partitions";
 195                         #address-cells = <1>;
 196                         #size-cells = <1>;
 197
 198                         partition0@0 {
 199                                 label = "SBL1";
 200                                 reg = <0x00000000 0x00040000>;
 201                                 read-only;
 202                         };
 203
 204                         partition1@40000 {
 205                                 label = "MIBIB";
 206                                 reg = <0x00040000 0x00020000>;
 207                                 read-only;
 208                         };
 209
 210                         partition2@60000 {
 211                                 label = "QSEE";
 212                                 reg = <0x00060000 0x00060000>;
 213                                 read-only;
 214                         };
 215
 216                         partition3@c0000 {
 217                                 label = "CDT";
 218                                 reg = <0x000c0000 0x00010000>;
 219                                 read-only;
 220                         };
 221
 222                         partition4@d0000 {
 223                                 label = "DDRPARAMS";
 224                                 reg = <0x000d0000 0x00010000>;
 225                                 read-only;
 226                         };
 227
 228                         partition5@E0000 {
 229                                 label = "APPSBLENV";
 230                                 reg = <0x000e0000 0x00010000>;
 231                                 read-only;
 232                         };
 233
 234                         partition6@F0000 {
 235                                 label = "APPSBL";
 236                                 reg = <0x000f0000 0x00080000>;
 237                                 read-only;
 238                         };
 239
 240                         partition7@170000 {
 241                                 label = "ART";
 242                                 reg = <0x00170000 0x00010000>;
 243                                 read-only;
 244
 245                                 nvmem-layout {
 246                                         compatible = "fixed-layout";
 247                                         #address-cells = <1>;
 248                                         #size-cells = <1>;
 249
 250                                         precal_art_1000: precal@1000 {
 251                                                 reg = <0x1000 0x2f20>;
 252                                         };
 253
 254                                         precal_art_5000: precal@5000 {
 255                                                 reg = <0x5000 0x2f20>;
 256                                         };
 257                                 };
 258                         };
 259
 260                         partition8@180000 {
 261                                 label = "config";
 262                                 reg = <0x00180000 0x00010000>;
 263                                 read-only;
 264                         };
 265
 266                         partition9@190000 {
 267                                 label = "pot";
 268                                 reg = <0x00190000 0x00010000>;
 269                                 read-only;
 270                         };
 271
 272                         partition10@1a0000 {
 273                                 label = "dnidata";
 274                                 reg = <0x001a0000 0x00010000>;
 275                                 read-only;
 276
 277                                 nvmem-layout {
 278                                         compatible = "fixed-layout";
 279                                         #address-cells = <1>;
 280                                         #size-cells = <1>;
 281
 282                                         macaddr_dnidata_0: macaddr@0 {
 283                                                 reg = <0x0 0x6>;
 284                                         };
 285
 286                                         macaddr_dnidata_c: macaddr@c {
 287                                                 reg = <0xc 0x6>;
 288                                         };
 289                                 };
 290                         };
 291
 292                         partition11@1b0000 {
 293                                 compatible = "denx,fit";
 294                                 label = "firmware";
 295                                 reg = <0x001b0000 0x00e10000>;
 296                         };
 297
 298                         partition12@fc0000 {
 299                                 label = "language";
 300                                 reg = <0x00fc0000 0x00040000>;
 301                                 read-only;
 302                         };
 303                 };
 304         };
 305 };
 306
 307 &blsp1_uart1 {
 308         pinctrl-0 = <&serial_pins>;
 309         pinctrl-names = "default";
 310         status = "okay";
 311 };
 312
 313 &blsp_dma {
 314         status = "okay";
 315 };
 316
 317 &cryptobam {
 318         status = "okay";
 319 };
 320
 321 &wifi0 {
 322         status = "okay";
 323         nvmem-cell-names = "pre-calibration", "mac-address";
 324         nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
 325 };
 326
 327 &wifi1 {
 328         status = "okay";
 329         nvmem-cell-names = "pre-calibration", "mac-address";
 330         nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
 331 };
 332
 333 &gmac {
 334         status = "okay";
 335 };
 336
 337 &switch {
 338         status = "okay";
 339 };
 340
 341 &swport4 {
 342         status = "okay";
 343         label = "lan";
 344 };