target/linux/bcm27xx/patches-6.1/950-0942-drm-vc4-hvs-Test-if-the-EOF-interrupts-are-enabled.patch

   1 From bcf02f6ac0d429a425e8409f140bd875a1feed2e Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 27 Apr 2023 13:46:53 +0200
   4 Subject: [PATCH] drm/vc4: hvs: Test if the EOF interrupts are enabled
   5
   6 We currently enable the EOF interrupts through the CRTC destroy_state
   7 implementation.
   8
   9 However, nothing guarantees that we can't call destroy_state multiple
  10 times in a row, and therefore before the EOF interrupt even happens.
  11
  12 This means we would enable the interrupt multiple times but disable it
  13 only once. It wasn't an issue so far since the interrupts were only
  14 enabled by setting a bit in a register, but with BCM2712 we will use an
  15 external interrupt controller, with a refcounted interrupt.
  16
  17 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  18 ---
  19  drivers/gpu/drm/vc4/vc4_drv.h |  8 ++++++--
  20  drivers/gpu/drm/vc4/vc4_hvs.c | 14 ++++++++++++--
  21  2 files changed, 18 insertions(+), 4 deletions(-)
  22
  23 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  24 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  25 @@ -333,6 +333,8 @@ struct vc4_v3d {
  26         struct debugfs_regset32 regset;
  27  };
  28
  29 +#define HVS_NUM_CHANNELS 3
  30 +
  31  struct vc4_hvs {
  32         struct vc4_dev *vc4;
  33         struct platform_device *pdev;
  34 @@ -341,6 +343,10 @@ struct vc4_hvs {
  35
  36         struct clk *core_clk;
  37
  38 +       struct {
  39 +               unsigned int enabled: 1;
  40 +       } eof_irq[HVS_NUM_CHANNELS];
  41 +
  42         unsigned long max_core_rate;
  43
  44         /* Memory manager for CRTCs to allocate space in the display
  45 @@ -373,8 +379,6 @@ struct vc4_hvs {
  46         bool vc5_hdmi_enable_4096by2160;
  47  };
  48
  49 -#define HVS_NUM_CHANNELS 3
  50 -
  51  struct vc4_hvs_state {
  52         struct drm_private_state base;
  53         unsigned long core_clock_rate;
  54 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  55 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  56 @@ -412,11 +412,14 @@ static void vc5_hvs_update_gamma_lut(str
  57         vc5_hvs_lut_load(hvs, vc4_crtc);
  58  }
  59
  60 -static void vc4_hvs_irq_enable_eof(const struct vc4_hvs *hvs,
  61 +static void vc4_hvs_irq_enable_eof(struct vc4_hvs *hvs,
  62                                    unsigned int channel)
  63  {
  64         struct vc4_dev *vc4 = hvs->vc4;
  65
  66 +       if (hvs->eof_irq[channel].enabled)
  67 +               return;
  68 +
  69         switch (vc4->gen) {
  70         case VC4_GEN_4:
  71                 HVS_WRITE(SCALER_DISPCTRL,
  72 @@ -433,13 +436,18 @@ static void vc4_hvs_irq_enable_eof(const
  73         default:
  74                 break;
  75         }
  76 +
  77 +       hvs->eof_irq[channel].enabled = true;
  78  }
  79
  80 -static void vc4_hvs_irq_clear_eof(const struct vc4_hvs *hvs,
  81 +static void vc4_hvs_irq_clear_eof(struct vc4_hvs *hvs,
  82                                   unsigned int channel)
  83  {
  84         struct vc4_dev *vc4 = hvs->vc4;
  85
  86 +       if (!hvs->eof_irq[channel].enabled)
  87 +               return;
  88 +
  89         switch (vc4->gen) {
  90         case VC4_GEN_4:
  91                 HVS_WRITE(SCALER_DISPCTRL,
  92 @@ -456,6 +464,8 @@ static void vc4_hvs_irq_clear_eof(const
  93         default:
  94                 break;
  95         }
  96 +
  97 +       hvs->eof_irq[channel].enabled = false;
  98  }
  99
 100  static struct vc4_hvs_dlist_allocation *