target/linux/ath79/dts/ar9344_qihoo_c301.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ar9344.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         model = "Qihoo 360 C301";
  10         compatible = "qihoo,c301";
  11
  12         aliases {
  13                 led-boot = &led_wlan_g;
  14                 led-failsafe = &led_wlan_o;
  15                 led-upgrade = &led_wlan_o;
  16         };
  17
  18         leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&jtag_disable_pins>;
  22
  23                 led_wlan_g: wlan_g {
  24                         label = "green:wlan";
  25                         gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
  26                 };
  27
  28                 led_wlan_o: wlan_o {
  29                         label = "orange:wlan";
  30                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  31                         linux,default-trigger = "phy1tpt";
  32                 };
  33         };
  34
  35         keys {
  36                 compatible = "gpio-keys";
  37
  38                 reset {
  39                         linux,code = <KEY_RESTART>;
  40                         gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  41                         debounce-interval = <60>;
  42                 };
  43         };
  44
  45         reg_eth_led_vbus {
  46                 compatible = "regulator-fixed";
  47                 regulator-name = "eth_led_vbus";
  48                 regulator-min-microvolt = <3300000>;
  49                 regulator-max-microvolt = <3300000>;
  50                 regulator-always-on;
  51                 gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
  52         };
  53
  54         usb_vbus: reg_usb_vbus {
  55                 compatible = "regulator-fixed";
  56                 regulator-name = "usb_vbus";
  57                 regulator-min-microvolt = <5000000>;
  58                 regulator-max-microvolt = <5000000>;
  59                 enable-active-high;
  60                 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
  61         };
  62 };
  63
  64 &pinmux {
  65         pmx_spi_cs1: pinmux_spi_cs1 {
  66                 pinctrl-single,bits = <0xc 0x07 0xff>;
  67         };
  68
  69         pmx_led_switch: pinmux_led_switch {
  70                 pinctrl-single,bits = <0x0 0x2b2a2d00 0xffffff00>;
  71         };
  72 };
  73
  74 &ref {
  75         clock-frequency = <40000000>;
  76 };
  77
  78 &gpio {
  79         gpio_ext_lna0 {
  80                 gpio-hog;
  81                 gpios = <14 0>;
  82                 output-high;
  83                 line-name = "c301:ext:lna0";
  84         };
  85
  86         gpio_ext_lna1 {
  87                 gpio-hog;
  88                 gpios = <15 0>;
  89                 output-high;
  90                 line-name = "c301:ext:lna1";
  91         };
  92 };
  93
  94 &builtin_switch {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pmx_led_switch>;
  97 };
  98
  99 &spi {
 100         status = "okay";
 101
 102         pinctrl-names = "default";
 103         pinctrl-0 = <&pmx_spi_cs1>;
 104
 105         flash@0 {
 106                 compatible = "jedec,spi-nor";
 107                 reg = <0>;
 108                 spi-max-frequency = <25000000>;
 109
 110                 partitions {
 111                         compatible = "fixed-partitions";
 112                         #address-cells = <1>;
 113                         #size-cells = <1>;
 114
 115                         uboot: partition@0 {
 116                                 label = "u-boot";
 117                                 reg = <0x0 0x40000>;
 118                                 read-only;
 119                         };
 120
 121                         partition@40000 {
 122                                 label = "u-boot-env";
 123                                 reg = <0x40000 0x10000>;
 124                                 read-only;
 125                         };
 126
 127                         partition@50000 {
 128                                 label = "devdata";
 129                                 reg = <0x50000 0x10000>;
 130                                 read-only;
 131                         };
 132
 133                         partition@60000 {
 134                                 label = "devconf";
 135                                 reg = <0x60000 0x10000>;
 136                                 read-only;
 137                         };
 138
 139                         partition@70000 {
 140                                 compatible = "seama";
 141                                 label = "firmware";
 142                                 reg = <0x70000 0xf60000>;
 143                         };
 144
 145                         partition@fd0000 {
 146                                 label = "warm_start";
 147                                 reg = <0xfd0000 0x10000>;
 148                                 read-only;
 149                         };
 150
 151                         partition@fe0000 {
 152                                 label = "action_image_config";
 153                                 reg = <0xfe0000 0x10000>;
 154                         };
 155
 156                         partition@ff0000 {
 157                                 label = "radiocfg";
 158                                 reg = <0xff0000 0x10000>;
 159                                 read-only;
 160
 161                                 nvmem-layout {
 162                                         compatible = "fixed-layout";
 163                                         #address-cells = <1>;
 164                                         #size-cells = <1>;
 165
 166                                         cal_radiocfg_5000: calibration@5000 {
 167                                                 reg = <0x5000 0x844>;
 168                                         };
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         flash@1 {
 175                 compatible = "jedec,spi-nor";
 176                 reg = <1>;
 177                 spi-max-frequency = <25000000>;
 178
 179                 partitions {
 180                         compatible = "fixed-partitions";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183
 184                         partition@0 {
 185                                 label = "firmware2";
 186                                 reg = <0x0 0xf00000>;
 187                         };
 188
 189                         partition@f00000 {
 190                                 label = "privatedata";
 191                                 reg = <0xf00000 0x100000>;
 192                                 read-only;
 193                         };
 194                 };
 195         };
 196 };
 197
 198 &usb {
 199         status = "okay";
 200 };
 201
 202 &usb_phy {
 203         status = "okay";
 204         phy-supply = <&usb_vbus>;
 205 };
 206
 207 &pcie {
 208         status = "okay";
 209
 210         wifi@0,0 {
 211                 compatible = "qcom,ath10k";
 212                 reg = <0 0 0 0 0>;
 213                 nvmem-cells = <&cal_radiocfg_5000>;
 214                 nvmem-cell-names = "calibration";
 215         };
 216 };
 217
 218 &wmac {
 219         status = "okay";
 220         qca,no-eeprom;
 221 };
 222
 223 &eth1 {
 224         status = "okay";
 225         gmac-config {
 226                 device = <&gmac>;
 227                 switch-phy-swap = <1>;
 228                 switch-only-mode = <1>;
 229         };
 230 };
 231
 232 &eth0 {
 233         status = "okay";
 234         phy-handle = <&swphy0>;
 235 };