mediatek: mt8183: add EMI MPU driver for DRAM protection
[project/bcm63xx/atf.git] / plat / mediatek / mt8183 / drivers / emi_mpu / emi_mpu.h
1 /*
2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef __EMI_MPU_H
8 #define __EMI_MPU_H
9
10 #include <platform_def.h>
11
12 #define EMI_MPUP (EMI_BASE + 0x01D8)
13 #define EMI_MPUQ (EMI_BASE + 0x01E0)
14 #define EMI_MPUR (EMI_BASE + 0x01E8)
15 #define EMI_MPUS (EMI_BASE + 0x01F0)
16 #define EMI_MPUT (EMI_BASE + 0x01F8)
17 #define EMI_MPUY (EMI_BASE + 0x0220)
18 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x0000)
19 #define EMI_MPUD0_ST (EMI_BASE + 0x0160)
20 #define EMI_MPUD1_ST (EMI_BASE + 0x0164)
21 #define EMI_MPUD2_ST (EMI_BASE + 0x0168)
22 #define EMI_MPUD3_ST (EMI_BASE + 0x016C)
23 #define EMI_MPUD0_ST2 (EMI_BASE + 0x0200)
24 #define EMI_MPUD1_ST2 (EMI_BASE + 0x0204)
25 #define EMI_MPUD2_ST2 (EMI_BASE + 0x0208)
26 #define EMI_MPUD3_ST2 (EMI_BASE + 0x020C)
27
28 #define EMI_PHY_OFFSET (0x40000000UL)
29 #define EIGHT_DOMAIN
30
31 #define NO_PROTECTION (0)
32 #define SEC_RW (1)
33 #define SEC_RW_NSEC_R (2)
34 #define SEC_RW_NSEC_W (3)
35 #define SEC_R_NSEC_R (4)
36 #define FORBIDDEN (5)
37 #define SEC_R_NSEC_RW (6)
38
39 #define SECURE_OS_MPU_REGION_ID (0)
40 #define ATF_MPU_REGION_ID (1)
41
42 #ifdef EIGHT_DOMAIN
43 #define SET_ACCESS_PERMISSON(d7, d6, d5, d4, d3, d2, d1, d0) \
44 (((d7) << 21) | ((d6) << 18) | ((d5) << 15) | ((d4) << 12) \
45 | ((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
46 #else
47 #define SET_ACCESS_PERMISSON(d3, d2, d1, d0) \
48 (((d3) << 9) | ((d2) << 6) | ((d1) << 3) | (d0))
49 #endif
50
51 //#define EMI_MPU_BASE (0x1020E000U)
52
53 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
54 #define EMI_MPU_SA1 (EMI_MPU_BASE + 0x104)
55 #define EMI_MPU_SA2 (EMI_MPU_BASE + 0x108)
56 #define EMI_MPU_SA3 (EMI_MPU_BASE + 0x10C)
57 #define EMI_MPU_SA4 (EMI_MPU_BASE + 0x110)
58 #define EMI_MPU_SA5 (EMI_MPU_BASE + 0x114)
59 #define EMI_MPU_SA6 (EMI_MPU_BASE + 0x118)
60 #define EMI_MPU_SA7 (EMI_MPU_BASE + 0x11C)
61
62 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
63 #define EMI_MPU_EA1 (EMI_MPU_BASE + 0x204)
64 #define EMI_MPU_EA2 (EMI_MPU_BASE + 0x208)
65 #define EMI_MPU_EA3 (EMI_MPU_BASE + 0x20C)
66 #define EMI_MPU_EA4 (EMI_MPU_BASE + 0x210)
67 #define EMI_MPU_EA5 (EMI_MPU_BASE + 0x214)
68 #define EMI_MPU_EA6 (EMI_MPU_BASE + 0x218)
69 #define EMI_MPU_EA7 (EMI_MPU_BASE + 0x21C)
70
71 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
72 #define EMI_MPU_APC1 (EMI_MPU_BASE + 0x304)
73 #define EMI_MPU_APC2 (EMI_MPU_BASE + 0x308)
74 #define EMI_MPU_APC3 (EMI_MPU_BASE + 0x30C)
75 #define EMI_MPU_APC4 (EMI_MPU_BASE + 0x310)
76 #define EMI_MPU_APC5 (EMI_MPU_BASE + 0x314)
77 #define EMI_MPU_APC6 (EMI_MPU_BASE + 0x318)
78 #define EMI_MPU_APC7 (EMI_MPU_BASE + 0x31C)
79
80 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
81 #define EMI_MPU_CTRL_D1 (EMI_MPU_BASE + 0x804)
82 #define EMI_MPU_CTRL_D2 (EMI_MPU_BASE + 0x808)
83 #define EMI_MPU_CTRL_D3 (EMI_MPU_BASE + 0x80C)
84 #define EMI_MPU_CTRL_D4 (EMI_MPU_BASE + 0x810)
85 #define EMI_MPU_CTRL_D5 (EMI_MPU_BASE + 0x814)
86 #define EMI_MPU_CTRL_D6 (EMI_MPU_BASE + 0x818)
87 #define EMI_MPU_CTRL_D7 (EMI_MPU_BASE + 0x81C)
88
89 #define EMI_MPU_MASK_D0 (EMI_MPU_BASE + 0x900)
90 #define EMI_MPU_MASK_D1 (EMI_MPU_BASE + 0x904)
91 #define EMI_MPU_MASK_D2 (EMI_MPU_BASE + 0x908)
92 #define EMI_MPU_MASK_D3 (EMI_MPU_BASE + 0x90C)
93 #define EMI_MPU_MASK_D4 (EMI_MPU_BASE + 0x910)
94 #define EMI_MPU_MASK_D5 (EMI_MPU_BASE + 0x914)
95 #define EMI_MPU_MASK_D6 (EMI_MPU_BASE + 0x918)
96 #define EMI_MPU_MASK_D7 (EMI_MPU_BASE + 0x91C)
97
98 int emi_mpu_set_region_protection(
99 unsigned long start, unsigned long end,
100 int region,
101 unsigned int access_permission);
102
103 void dump_emi_mpu_regions(void);
104 void emi_mpu_init(void);
105
106 #endif /* __EMI_MPU_H */