Add Broadcom's code for bcm63xx support
[project/bcm63xx/atf.git] / plat / bcm / include / pmc_addr_6858.h
1 /*
2 <:copyright-BRCM:2019:DUAL/GPL:standard
3
4 Copyright (c) 2019 Broadcom
5 All Rights Reserved
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License, version 2, as published by
9 the Free Software Foundation (the "GPL").
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16
17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA.
20
21 :>
22 */
23
24 #ifndef PMC_ADDR_6858_H__
25 #define PMC_ADDR_6858_H__
26
27 #define PMB_BUS_MAX 2
28 #define PMB_BUS_ID_SHIFT 8
29
30 #define PMB_BUS_PERIPH 0
31 #define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
32 #define PMB_ZONES_PERIPH 3
33
34 #define PMB_BUS_CHIP_CLKRST 0
35 #define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
36 #define PMB_ZONES_CHIP_CLKRST 0
37
38 #define PMB_BUS_SYSPLL 0
39 #define PMB_ADDR_SYSPLL (2 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
40 #define PMB_ZONES_SYSPLL 0
41
42 #define PMB_BUS_RDPPLL 0
43 #define PMB_ADDR_RDPPLL (3 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
44 #define PMB_ZONES_RDPPLL 0
45
46 #define PMB_BUS_UNIPLL 0
47 #define PMB_ADDR_UNIPLL (5 | PMB_BUS_UNIPLL << PMB_BUS_ID_SHIFT)
48 #define PMB_ZONES_UNIPLL 0
49
50 #define PMB_BUS_CRYPTO 1
51 #define PMB_ADDR_CRYPTO (6 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
52 #define PMB_ZONES_CRYPTO 0
53
54 #define PMB_BUS_APM 0
55 #define PMB_ADDR_APM (7 | PMB_BUS_APM << PMB_BUS_ID_SHIFT)
56 #define PMB_ZONES_APM 2
57
58 #define PMB_BUS_MEMC 0
59 #define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
60 #define PMB_ZONES_MEMC 1
61
62 #define PMB_BUS_LPORT 1
63 #define PMB_ADDR_LPORT (9 | PMB_BUS_LPORT << PMB_BUS_ID_SHIFT)
64 #define PMB_ZONES_LPORT 3
65
66 #define PMB_BUS_USB30_2X 1
67 #define PMB_ADDR_USB30_2X (10 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
68 #define PMB_ZONES_USB30_2X 4
69
70 #define PMB_BUS_WAN 1
71 #define PMB_ADDR_WAN (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT)
72 #define PMB_ZONES_WAN 7
73
74 #define PMB_BUS_XRDP 1
75 #define PMB_ADDR_XRDP (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
76 #define PMB_ZONES_XRDP 3
77
78 #define PMB_BUS_XRDP_QM 1
79 #define PMB_ADDR_XRDP_QM (13 | PMB_BUS_XRDP_QM << PMB_BUS_ID_SHIFT)
80 #define PMB_ZONES_XRDP_QM 1
81
82 #define PMB_BUS_XRDP_RC_QUAD0 1
83 #define PMB_ADDR_XRDP_RC_QUAD0 (14 | PMB_BUS_XRDP_RC_QUAD0 << PMB_BUS_ID_SHIFT)
84 #define PMB_ZONES_XRDP_RC_QUAD0 1
85
86 #define PMB_BUS_XRDP_RC_QUAD1 1
87 #define PMB_ADDR_XRDP_RC_QUAD1 (15 | PMB_BUS_XRDP_RC_QUAD1 << PMB_BUS_ID_SHIFT)
88 #define PMB_ZONES_XRDP_RC_QUAD1 1
89
90 #define PMB_BUS_XRDP_RC_QUAD2 1
91 #define PMB_ADDR_XRDP_RC_QUAD2 (16 | PMB_BUS_XRDP_RC_QUAD2 << PMB_BUS_ID_SHIFT)
92 #define PMB_ZONES_XRDP_RC_QUAD2 1
93
94 #define PMB_BUS_XRDP_RC_QUAD3 1
95 #define PMB_ADDR_XRDP_RC_QUAD3 (17 | PMB_BUS_XRDP_RC_QUAD3 << PMB_BUS_ID_SHIFT)
96 #define PMB_ZONES_XRDP_RC_QUAD3 1
97
98 #define PMB_BUS_PCIE0 1
99 #define PMB_ADDR_PCIE0 (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
100 #define PMB_ZONES_PCIE0 1
101
102 #define PMB_BUS_PCIE1 1
103 #define PMB_ADDR_PCIE1 (19 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
104 #define PMB_ZONES_PCIE1 1
105
106 #define PMB_BUS_SATA 1
107 #define PMB_ADDR_SATA (20 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
108 #define PMB_ZONES_SATA 1
109
110 #define PMB_BUS_PCIE_UBUS 1
111 #define PMB_ADDR_PCIE_UBUS (21 | PMB_BUS_PCIE_UBUS << PMB_BUS_ID_SHIFT)
112 #define PMB_ZONES_PCIE_UBUS 1
113
114 #define PMB_BUS_ORION_CPU0 0
115 #define PMB_ADDR_ORION_CPU0 (24 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
116 #define PMB_ZONES_ORION_CPU0 1
117
118 #define PMB_BUS_ORION_CPU1 0
119 #define PMB_ADDR_ORION_CPU1 (25 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
120 #define PMB_ZONES_ORION_CPU1 1
121
122 #define PMB_BUS_ORION_CPU2 0
123 #define PMB_ADDR_ORION_CPU2 (26 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
124 #define PMB_ZONES_ORION_CPU2 1
125
126 #define PMB_BUS_ORION_CPU3 0
127 #define PMB_ADDR_ORION_CPU3 (27 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
128 #define PMB_ZONES_ORION_CPU3 1
129
130 #define PMB_BUS_ORION_NONCPU 0
131 #define PMB_ADDR_ORION_NONCPU (28 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
132 #define PMB_ZONES_ORION_NONCPU 1
133
134 #define PMB_BUS_ORION_ARS 0
135 #define PMB_ADDR_ORION_ARS (29 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
136 #define PMB_ZONES_ORION_ARS 1
137
138 #define PMB_BUS_BIU_PLL 0
139 #define PMB_ADDR_BIU_PLL (30 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
140 #define PMB_ZONES_BIU_PLL 1 // FIXMET
141
142 #define PMB_BUS_BIU_BPCM 0
143 #define PMB_ADDR_BIU_BPCM (31 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
144 #define PMB_ZONES_BIU_BPCM 1
145
146 #define PMB_BUS_PCM 0
147
148 #define PMB_ADDR_PCM (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
149
150 #define PMB_ZONES_PCM 2
151 enum {
152 PCM_Zone_Main,
153 PCM_Zone_PCM = 3,
154 };
155 //--------- SOFT Reset bits for PCM ------------------------
156 #define BPCM_PCM_SRESET_HARDRST_N 0x00000004
157
158 #define BPCM_PCM_SRESET_PCM_N 0x00000040
159
160 #define BPCM_PCM_SRESET_BUS_N 0x00000001
161
162 #endif