plat/bcm/include/pmc_addr_63178.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef PMC_ADDR_63178_H__
  25 #define PMC_ADDR_63178_H__
  26
  27 #define PMB_BUS_ID_SHIFT         12
  28
  29 #define PMB_BUS_PERIPH           0
  30 #define PMB_ADDR_PERIPH          (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  31 #define PMB_ZONES_PERIPH         4
  32
  33 #define PMB_BUS_CHIP_CLKRST      0
  34 #define PMB_ADDR_CHIP_CLKRST     (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  35 #define PMB_ZONES_CHIP_CLKRST    0
  36
  37 #define BPCM_CLKRST_AFE_PWRDWN   0x20000000
  38
  39 #define PMB_BUS_AFEPLL           0
  40 #define PMB_ADDR_AFEPLL          (2 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT)
  41 #define PMB_ZONES_AFEPLL         0
  42
  43 #define AFEPLL_PMB_BUS_VDSL3_CORE       PMB_BUS_AFEPLL
  44 #define AFEPLL_PMB_ADDR_VDSL3_CORE      PMB_ADDR_AFEPLL
  45 #define AFEPLL_PMB_ZONES_VDSL3_CORE     PMB_ZONES_AFEPLL
  46
  47 #define PMB_BUS_PVTMON           0
  48 #define PMB_ADDR_PVTMON          (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
  49 #define PMB_ZONES_PVTMON         0
  50
  51 #define PMB_BUS_SWITCH           0
  52 #define PMB_ADDR_SWITCH          (4 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
  53 #define PMB_ZONES_SWITCH         4
  54
  55 #define PMB_BUS_USB30_2X         0
  56 #define PMB_ADDR_USB30_2X        (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
  57 #define PMB_ZONES_USB30_2X       4
  58
  59 #define PMB_BUS_PCIE0            1
  60 #define PMB_ADDR_PCIE0           (6 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
  61 #define PMB_ZONES_PCIE0          1
  62
  63 #define PMB_BUS_VDSL3_CORE       1
  64 #define PMB_ADDR_VDSL3_CORE      (7 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
  65 #define PMB_ZONES_VDSL3_CORE     2
  66
  67 #define PMB_BUS_VDSL3_MIPS       PMB_BUS_VDSL3_CORE
  68 #define PMB_ADDR_VDSL3_MIPS      PMB_ADDR_VDSL3_CORE
  69 #define PMB_ZONES_VDSL3_MIPS     PMB_ZONES_VDSL3_CORE
  70
  71 //--------- DGASP related bits/Offsets ------------------------
  72 #define BPCM_PHY_CNTL_OVERRIDE         0x08000000
  73 #define PMB_ADDR_VDSL_DGASP_PMD        PMB_ADDR_VDSL3_CORE
  74 #define BPCM_VDSL_PHY_CTL_REG          vdsl_phy_ctl     // Alias for register containing DGASP override inside the VDSL PMD
  75 #define BPCM_VDSL_AFE_CTL_REG          vdsl_afe_ctl     // Alias for register containing DGASP configuration inside the VDSL PMD
  76
  77 #define PMB_BUS_MEMC             1
  78 #define PMB_ADDR_MEMC            (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  79 #define PMB_ZONES_MEMC           1
  80
  81 #define PMB_BUS_WLAN0_PHY1       0
  82 #define PMB_ADDR_WLAN0_PHY1      (9 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT)
  83 #define PMB_ZONES_WLAN0_PHY1     1
  84
  85 #define PMB_BUS_WLAN0_PHY2       0
  86 #define PMB_ADDR_WLAN0_PHY2      (10 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT)
  87 #define PMB_ZONES_WLAN0_PHY2     1
  88
  89 #define PMB_BUS_WLAN0            0
  90 #define PMB_ADDR_WLAN0           (11 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT)
  91 #define PMB_ZONES_WLAN0          1
  92
  93 #define PMB_BUS_ORION_CPU0       1
  94 #define PMB_ADDR_ORION_CPU0      (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
  95 #define PMB_ZONES_ORION_CPU0     1
  96
  97 #define PMB_BUS_ORION_CPU1       1
  98 #define PMB_ADDR_ORION_CPU1      (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
  99 #define PMB_ZONES_ORION_CPU1     1
 100
 101 #define PMB_BUS_ORION_CPU2       1
 102 #define PMB_ADDR_ORION_CPU2      (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
 103 #define PMB_ZONES_ORION_CPU2     1
 104
 105 #define PMB_BUS_ORION_NONCPU     1
 106 #define PMB_ADDR_ORION_NONCPU    (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
 107 #define PMB_ZONES_ORION_NONCPU   1
 108
 109 #define PMB_BUS_BIU_PLL          1
 110 #define PMB_ADDR_BIU_PLL         (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
 111 #define PMB_ZONES_BIU_PLL        0
 112
 113 #define PMB_BUS_BIU_BPCM         1
 114 #define PMB_ADDR_BIU_BPCM        (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
 115 #define PMB_ZONES_BIU_BPCM       1
 116
 117 #define PMB_BUS_PCM              PMB_BUS_PERIPH
 118 #define PMB_ADDR_PCM             (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT)
 119 #define PMB_ZONES_PCM            4
 120
 121 enum {
 122         PCM_Zone_Main,
 123         PCM_Zone_PCM = 3
 124 };
 125 //--------- SOFT Reset bits for PCM ------------------------
 126 #define   BPCM_PCM_SRESET_PCM_N       0x00000040
 127
 128 #define RCAL_0P25UM_HORZ          0
 129 #define RCAL_0P25UM_VERT          1
 130 #define RCAL_0P5UM_HORZ           2
 131 #define RCAL_0P5UM_VERT           3
 132 #define RCAL_1UM_HORZ             4
 133 #define RCAL_1UM_VERT             5
 134 #define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
 135 #define PMMISC_RMON_VALID_MASK    (0x1<<16)
 136
 137 #endif