plat/bcm/include/pmc_addr_63146.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef PMC_ADDR_63146_H__
  25 #define PMC_ADDR_63146_H__
  26
  27 /* FIXME! only fill those that I found from RTL */
  28 #define PMB_BUS_MAX             2
  29 #define PMB_BUS_ID_SHIFT        12
  30
  31 #define PMB_BUS_PCIE0           0
  32 #define PMB_ADDR_PCIE0          (0 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
  33 #define PMB_ZONES_PCIE0         1
  34
  35 #define PMB_BUS_VDSL3_CORE      0
  36 #define PMB_ADDR_VDSL3_CORE     (1 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
  37 #define PMB_ZONES_VDSL3_CORE    1
  38
  39 #define PMB_BUS_EGPHY           0
  40 #define PMB_ADDR_EGPHY          (2 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT)
  41 #define PMB_ZONES_EGPHY         1       // not shown in spreadsheet
  42
  43 #define PMB_BUS_XRDP            0
  44 #define PMB_ADDR_XRDP           (3 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
  45 #define PMB_ZONES_XRDP          3
  46
  47 #define PMB_BUS_USB30_2X        0
  48 #define PMB_ADDR_USB30_2X       (4 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
  49 #define PMB_ZONES_USB30_2X      4
  50
  51 #define PMB_BUS_MEMC            0
  52 #define PMB_ADDR_MEMC           (5 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  53 #define PMB_ZONES_MEMC          1
  54
  55 #define PMB_BUS_PVTMON          0
  56 #define PMB_ADDR_PVTMON         (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
  57 #define PMB_ZONES_PVTMON        0
  58
  59 #define PMB_BUS_PCIE1           0
  60 #define PMB_ADDR_PCIE1          (7 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
  61 #define PMB_ZONES_PCIE1         1
  62
  63 #define PMB_BUS_PCIE2           0
  64 #define PMB_ADDR_PCIE2          (8 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
  65 #define PMB_ZONES_PCIE2         1
  66
  67 #define PMB_BUS_PERIPH          1
  68 #define PMB_ADDR_PERIPH         (9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  69 #define PMB_ZONES_PERIPH        4
  70
  71 #define PMB_BUS_VDSL3_PMD       1
  72 #define PMB_ADDR_VDSL3_PMD      (10 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT)
  73 #define PMB_ZONES_VDSL3_PMD     1
  74
  75 //--------- DGASP related bits/Offsets ------------------------
  76 #define BPCM_PHY_CNTL_OVERRIDE          0x00000002
  77 #define BPCM_PHY_CNTL_AFE_PWRDWN        0x00000001
  78 #define PMB_ADDR_VDSL_DGASP_PMD         PMB_ADDR_VDSL3_PMD
  79 #define BPCM_VDSL_PHY_CTL_REG           vdsl_afe_config1        // Alias for register containing DGASP override inside the VDSL PMD
  80 #define BPCM_VDSL_AFE_CTL_REG           vdsl_afe_config0        // Alias for register containing DGASP configuration inside the VDSL PMD
  81
  82 #define PMB_BUS_AFEPLL          1
  83 #define PMB_ADDR_AFEPLL         (11 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT)
  84 #define PMB_ZONES_AFEPLL        1
  85
  86 #define AFEPLL_PMB_BUS_VDSL3_CORE       PMB_BUS_AFEPLL
  87 #define AFEPLL_PMB_ADDR_VDSL3_CORE      PMB_ADDR_AFEPLL
  88 #define AFEPLL_PMB_ZONES_VDSL3_CORE     PMB_ZONES_AFEPLL
  89
  90 #define PMB_BUS_CHIP_CLKRST     1
  91 #define PMB_ADDR_CHIP_CLKRST    (12 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  92 #define PMB_ZONES_CHIP_CLKRST   0
  93
  94 #define PMB_BUS_RDPPLL          1
  95 #define PMB_ADDR_RDPPLL         (13 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
  96 #define PMB_ZONES_RDPPLL        0
  97
  98 #define PMB_BUS_BIU_PLL         1
  99 #define PMB_ADDR_BIU_PLL        (32 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT)
 100 #define PMB_ZONES_BIU_PLL       0
 101
 102 #define PMB_BUS_BIU_BPCM        1
 103 #define PMB_ADDR_BIU_BPCM       (33 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT)
 104 #define PMB_ZONES_BIU_BPCM      1
 105
 106 #define PMB_BUS_ORION_CPU0      1
 107 #define PMB_ADDR_ORION_CPU0     (34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
 108 #define PMB_ZONES_ORION_CPU0    1
 109
 110 #define PMB_BUS_ORION_CPU1      1
 111 #define PMB_ADDR_ORION_CPU1     (35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
 112 #define PMB_ZONES_ORION_CPU1    1
 113
 114 #define PMB_BUS_ORION_NONCPU    1
 115 #define PMB_ADDR_ORION_NONCPU   (38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
 116 #define PMB_ZONES_ORION_NONCPU  1
 117
 118 #define PMB_BUS_ORION_ARS       1
 119 #define PMB_ADDR_ORION_ARS      (39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
 120 #define PMB_ZONES_ORION_ARS     0
 121
 122 #endif