plat/bcm/include/pmc_addr_63138.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef PMC_ADDR_63138_H__
  25 #define PMC_ADDR_63138_H__
  26
  27 #define PMB_BUS_MAX                     2
  28 #define PMB_BUS_ID_SHIFT                8
  29
  30 #define PMB_BUS_APM                     1
  31 #define PMB_ADDR_APM                    (0 | PMB_BUS_APM << PMB_BUS_ID_SHIFT)
  32 #define PMB_ZONES_APM                   5
  33
  34 //--------- SOFT Reset bits for APM ------------------------
  35 #define   BPCM_APM_SRESET_HARDRST_N   0x00000040
  36 #define   BPCM_APM_SRESET_AUDIO_N     0x00000020
  37 #define   BPCM_APM_SRESET_PCM_N       0x00000010
  38 #define   BPCM_APM_SRESET_HVGA_N      0x00000008
  39 #define   BPCM_APM_SRESET_HVGB_N      0x00000004
  40 #define   BPCM_APM_SRESET_BMU_N       0x00000002
  41 #define   BPCM_APM_SRESET_200_N       0x00000001
  42
  43 #define PMB_BUS_SWITCH                  1
  44 #define PMB_ADDR_SWITCH                 (1 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
  45 #define PMB_ZONES_SWITCH                3
  46
  47 #define PMB_BUS_CHIP_CLKRST             1
  48 #define PMB_ADDR_CHIP_CLKRST            (2 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  49 #define PMB_ZONES_CHIP_CLKRST           0
  50
  51 #define PMB_BUS_SATA                    0
  52 #define PMB_ADDR_SATA                   (3 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
  53 #define PMB_ZONES_SATA                  1
  54
  55 #define PMB_BUS_AIP                     0
  56 #define PMB_ADDR_AIP                    (4 | PMB_BUS_AIP << PMB_BUS_ID_SHIFT)
  57 #define PMB_ZONES_AIP                   1
  58
  59 #define PMB_BUS_DECT_UBUS               0
  60 #define PMB_ADDR_DECT_UBUS              (5 | PMB_BUS_DECT_UBUS << PMB_BUS_ID_SHIFT)
  61 #define PMB_ZONES_DECT_UBUS             1
  62
  63 #define PMB_BUS_SAR                     1
  64 #define PMB_ADDR_SAR                    (6 | PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
  65 #define PMB_ZONES_SAR                   1
  66
  67 #define PMB_BUS_RDP                     1
  68 #define PMB_ADDR_RDP                    (7 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT)
  69 #define PMB_ZONES_RDP                   2
  70
  71 #define PMB_BUS_MEMC                    0
  72 #define PMB_ADDR_MEMC                   (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  73 #define PMB_ZONES_MEMC                  1
  74
  75 #define PMB_BUS_PERIPH                  0
  76 #define PMB_ADDR_PERIPH                 (9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  77 #define PMB_ZONES_PERIPH                3
  78
  79 #define PMB_BUS_SYSPLL                  1
  80 #define PMB_ADDR_SYSPLL                 (10 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT)
  81 #define PMB_ZONES_SYSPLL                0
  82
  83 #define PMB_BUS_RDPPLL                  1
  84 #define PMB_ADDR_RDPPLL                 (11 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT)
  85 #define PMB_ZONES_RDPPLL                0
  86
  87 #define PMB_BUS_SYSPLL2                 0
  88 #define PMB_ADDR_SYSPLL2                (12 | PMB_BUS_SYSPLL2 << PMB_BUS_ID_SHIFT)
  89 #define PMB_ZONES_SYSPLL2               0
  90
  91 #define PMB_BUS_SYSPLL3                 0
  92 #define PMB_ADDR_SYSPLL3                (13 | PMB_BUS_SYSPLL3 << PMB_BUS_ID_SHIFT)
  93 #define PMB_ZONES_SYSPLL3               0
  94
  95 #define PMB_BUS_SYSPLL4                 0
  96 #define PMB_ADDR_SYSPLL4                (14 | PMB_BUS_SYSPLL4 << PMB_BUS_ID_SHIFT)
  97 #define PMB_ZONES_SYSPLL4               0
  98
  99 #define PMB_BUS_PCIE0                   0
 100 #define PMB_ADDR_PCIE0                  (15 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
 101 #define PMB_ZONES_PCIE0                 1
 102
 103 #define PMB_BUS_PCIE1                   0
 104 #define PMB_ADDR_PCIE1                  (16 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
 105 #define PMB_ZONES_PCIE1                 1
 106
 107 #define PMB_BUS_USB30_2X                1
 108 #define PMB_ADDR_USB30_2X               (17 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
 109 #define PMB_ZONES_USB30_2X              4
 110
 111 #define PMB_BUS_PSAB                    0
 112 #define PMB_ADDR_PSAB                   (18 | PMB_BUS_PSAB << PMB_BUS_ID_SHIFT)
 113 #define PMB_ZONES_PSAB                  1       // not shown in spreadsheet
 114
 115 #define PMB_BUS_PSBC                    0
 116 #define PMB_ADDR_PSBC                   (19 | PMB_BUS_PSBC << PMB_BUS_ID_SHIFT)
 117 #define PMB_ZONES_PSBC                  1       // not shown in spreadsheet
 118
 119 #define PMB_BUS_EGPHY                   0
 120 #define PMB_ADDR_EGPHY                  (20 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT)
 121 #define PMB_ZONES_EGPHY                 1       // not shown in spreadsheet
 122
 123 #define PMB_BUS_VDSL3_MIPS              0
 124 #define PMB_ADDR_VDSL3_MIPS             (21 | PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
 125 #define PMB_ZONES_VDSL3_MIPS            1
 126
 127 #define PMB_BUS_VDSL3_CORE              0
 128 #define PMB_ADDR_VDSL3_CORE             (22 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
 129 #define PMB_ZONES_VDSL3_CORE            3
 130
 131 #define AFEPLL_PMB_BUS_VDSL3_CORE       0
 132 #define AFEPLL_PMB_ADDR_VDSL3_CORE      (23 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
 133 #define AFEPLL_PMB_ZONES_VDSL3_CORE     0
 134
 135 #define UBUS_PMB_BUS_VDSL3_CORE         PMB_BUS_VDSL3_CORE
 136 #define UBUS_PMB_ADDR_VDSL3_CORE        (24 | UBUS_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT)
 137 #define UBUS_PMB_ZONES_VDSL3_CORE       0
 138
 139 #define UBUS_PMB_BUS_VDSL3_MIPS         PMB_BUS_VDSL3_MIPS
 140 #define UBUS_PMB_ADDR_VDSL3_MIPS        (25 | UBUS_PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT)
 141 #define UBUS_PMB_ZONES_VDSL3_MIPS       0
 142
 143 #define UBUS_PMB_BUS_DECT               PMB_BUS_DECT_UBUS
 144 #define UBUS_PMB_ADDR_DECT              (26 | UBUS_PMB_BUS_DECT << PMB_BUS_ID_SHIFT)
 145 #define UBUS_PMB_ZONES_DECT             0
 146
 147 #define UBUS_PMB_BUS_ARM                PMB_BUS_AIP
 148 #define UBUS_PMB_ADDR_ARM               (27 | UBUS_PMB_BUS_ARM << PMB_BUS_ID_SHIFT)
 149 #define UBUS_PMB_ZONES_ARM              0
 150
 151 #define UBUS_PMB_BUS_DAP                PMB_BUS_AIP
 152 #define UBUS_PMB_ADDR_DAP               (28 | UBUS_PMB_BUS_DAP << PMB_BUS_ID_SHIFT)
 153 #define UBUS_PMB_ZONES_DAP              0
 154
 155 #define UBUS_CFG0_PMB_BUS_SAR           PMB_BUS_SAR
 156 #define UBUS_CFG0_PMB_ADDR_SAR          (29 | UBUS_CFG0_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
 157 #define UBUS_CFG0_PMB_ZONES_SAR         0
 158
 159 #define UBUS_CFG1_PMB_BUS_SAR           PMB_BUS_SAR
 160 #define UBUS_CFG1_PMB_ADDR_SAR          (30 | UBUS_CFG1_PMB_BUS_SAR << PMB_BUS_ID_SHIFT)
 161 #define UBUS_CFG1_PMB_ZONES_SAR         0
 162
 163 #define UBUS_CFG_PMB_BUS_DBR            PMB_BUS_RDP
 164 #define UBUS_CFG_PMB_ADDR_DBR           (31 | UBUS_CFG_PMB_BUS_DBR << PMB_BUS_ID_SHIFT)
 165 #define UBUS_CFG_PMB_ZONES_DBR          0
 166
 167 #define UBUS_CFG_PMB_BUS_RABR           PMB_BUS_RDP
 168 #define UBUS_CFG_PMB_ADDR_RABR          (32 | UBUS_CFG_PMB_BUS_RABR << PMB_BUS_ID_SHIFT)
 169 #define UBUS_CFG_PMB_ZONES_RABR         0
 170
 171 #define UBUS_CFG_PMB_BUS_RBBR           PMB_BUS_RDP
 172 #define UBUS_CFG_PMB_ADDR_RBBR          (33 | UBUS_CFG_PMB_BUS_RBBR << PMB_BUS_ID_SHIFT)
 173 #define UBUS_CFG_PMB_ZONES_RBBR         0
 174
 175 #define UBUS_CFG_PMB_BUS_APM            PMB_BUS_APM
 176 #define UBUS_CFG_PMB_ADDR_APM           (34 | UBUS_CFG_PMB_BUS_APM << PMB_BUS_ID_SHIFT)
 177 #define UBUS_CFG_PMB_ZONES_APM          0
 178
 179 #define UBUS_CFG_PMB_BUS_PCIE0          PMB_BUS_PCIE0
 180 #define UBUS_CFG_PMB_ADDR_PCIE0         (35 | UBUS_CFG_PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
 181 #define UBUS_CFG_PMB_ZONES_PCIE0        0
 182
 183 #define UBUS_CFG_PMB_BUS_PCIE1          PMB_BUS_PCIE1
 184 #define UBUS_CFG_PMB_ADDR_PCIE1         (36 | UBUS_CFG_PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
 185 #define UBUS_CFG_PMB_ZONES_PCIE1        0
 186
 187 #define UBUS_CFG_PMB_BUS_USBH           PMB_BUS_USB30_2X
 188 #define UBUS_CFG_PMB_ADDR_USBH          (37 | UBUS_CFG_PMB_BUS_USBH << PMB_BUS_ID_SHIFT)
 189 #define UBUS_CFG_PMB_ZONES_USBH         0
 190
 191 #define UBUS_CFG_PMB_BUS_USBD           PMB_BUS_USB30_2X
 192 #define UBUS_CFG_PMB_ADDR_USBD          (38 | UBUS_CFG_PMB_BUS_USBD << PMB_BUS_ID_SHIFT)
 193 #define UBUS_CFG_PMB_ZONES_USBD         0
 194
 195 #define UBUS_CFG_PMB_BUS_SWITCH         PMB_BUS_SWITCH
 196 #define UBUS_CFG_PMB_ADDR_SWITCH        (39 | UBUS_CFG_PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT)
 197 #define UBUS_CFG_PMB_ZONES_SWITCH       0
 198
 199 #define UBUS_CFG_PMB_BUS_PERIPH         PMB_BUS_PERIPH
 200 #define UBUS_CFG_PMB_ADDR_PERIPH        (40 | UBUS_CFG_PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
 201 #define UBUS_CFG_PMB_ZONES_PERIPH       0
 202
 203 #define UBUS_CFG_PMB_BUS_SATA           PMB_BUS_SATA
 204 #define UBUS_CFG_PMB_ADDR_SATA          (41 | UBUS_CFG_PMB_BUS_SATA << PMB_BUS_ID_SHIFT)
 205 #define UBUS_CFG_PMB_ZONES_SATA         0
 206
 207 /* define Zone enum for each block here */
 208 #ifndef _LANGUAGE_ASSEMBLY
 209 enum {
 210         APM_Zone_Main,
 211         APM_Zone_Audio,
 212         APM_Zone_PCM,
 213         APM_Zone_HVG,
 214         APM_Zone_BMU,
 215 };
 216 #endif
 217
 218 #endif