plat/bcm/include/bcm963xx/6813_map_part.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 Unless you and Broadcom execute a separate written software license
   8 agreement governing use of this software, this software is licensed
   9 to you under the terms of the GNU General Public License version 2
  10 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
  11 with the following added to such license:
  12
  13    As a special exception, the copyright holders of this software give
  14    you permission to link this software with independent modules, and
  15    to copy and distribute the resulting executable under terms of your
  16    choice, provided that you also meet, for each linked independent
  17    module, the terms and conditions of the license of that module.
  18    An independent module is a module which is not derived from this
  19    software.  The special exception does not apply to any modifications
  20    of the software.
  21
  22 Not withstanding the above, under no circumstances may you combine
  23 this software in any way with any other Broadcom software provided
  24 under a license other than the GPL, without Broadcom's express prior
  25 written consent.
  26
  27 :>
  28 */
  29
  30 #ifndef __BCM6813_MAP_PART_H
  31 #define __BCM6813_MAP_PART_H
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "bcmtypes.h"
  38
  39 #define MEMC_PHYS_BASE        0x80040000  /* MC2 TOP */
  40 #define MEMC_SIZE             0x00040000
  41
  42 #define PMC_PHYS_BASE         0xffa00000
  43 #define PMC_SIZE              0x00200000
  44 #define PMC_OFFSET            0x00100000
  45 #define PROC_MON_OFFSET       0x00100000
  46 #define PMB_OFFSET            0x00120100
  47
  48
  49 /* Perf block base address and size */
  50 #define PERF_PHYS_BASE        0xff800000
  51 #define PERF_SIZE             0x3500
  52 #define TIMR_OFFSET           0x0400   /* 64 bit timer registers */
  53 #define WDTIMR0_OFFSET        0x0480
  54 #define WDTIMR1_OFFSET        0x04c0
  55
  56
  57 #define BIUCFG_PHYS_BASE     0x81060000
  58 #define BIUCFG_SIZE          0x3000
  59 #define BIUCFG_OFFSET        0x0000
  60
  61 #define GIC_PHYS_BASE        0x81000000
  62 #define GIC_SIZE             0x10000
  63 #define GIC_OFFSET           0x0000
  64 #define GICD_OFFSET          0x1000
  65 #define GICC_OFFSET          0x2000
  66
  67 #define PMC_BASE           (PMC_PHYS_BASE + PMC_OFFSET)
  68 #define PROC_MON_BASE      (PMC_PHYS_BASE + PROC_MON_OFFSET)
  69 #define PMB_BASE           (PMC_PHYS_BASE+ PMB_OFFSET)
  70 #define BIUCFG_BASE        (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  71 #define WDTIMR0_BASE       (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  72
  73 #ifndef __ASSEMBLER__
  74 /*
  75  * Power Management Control
  76  */
  77 typedef struct PmcCtrlReg {
  78     uint32 gpTmr0Ctl;           /* 0x018 */
  79     uint32 gpTmr0Cnt;           /* 0x01c */
  80     uint32 gpTmr1Ctl;           /* 0x020 */
  81     uint32 gpTmr1Cnt;           /* 0x024 */
  82     uint32 hostMboxIn;          /* 0x028 */
  83     uint32 hostMboxOut;         /* 0x02c */
  84     uint32 reserved[4];         /* 0x030 */
  85     uint32 dmaCtrl;             /* 0x040 */
  86     uint32 dmaStatus;           /* 0x044 */
  87     uint32 dma0_3FifoStatus;    /* 0x048 */
  88     uint32 reserved1[4];            /* 0x04c */
  89     uint32 diagControl;         /* 0x05c */
  90     uint32 diagHigh;            /* 0x060 */
  91     uint32 diagLow;             /* 0x064 */
  92     uint32 reserved8;           /* 0x068 */
  93     uint32 addr1WndwMask;       /* 0x06c */
  94     uint32 addr1WndwBaseIn;     /* 0x070 */
  95     uint32 addr1WndwBaseOut;    /* 0x074 */
  96     uint32 addr2WndwMask;       /* 0x078 */
  97     uint32 addr2WndwBaseIn;     /* 0x07c */
  98     uint32 addr2WndwBaseOut;    /* 0x080 */
  99     uint32 scratch;             /* 0x084 */
 100     uint32 reserved9;           /* 0x088 */
 101     uint32 softResets;          /* 0x08c */
 102     uint32 reserved2;           /* 0x090 */
 103     uint32 m4keCoreStatus;      /* 0x094 */
 104     uint32 reserved3;           /* 0x098 */
 105     uint32 ubSlaveTimeout;      /* 0x09c */
 106     uint32 diagEn;              /* 0x0a0 */
 107     uint32 devTimeout;          /* 0x0a4 */
 108     uint32 ubusErrorOutMask;    /* 0x0a8 */
 109     uint32 diagCaptStopMask;    /* 0x0ac */
 110     uint32 revId;               /* 0x0b0 */
 111     uint32 reserved4[4];        /* 0x0b4 */
 112     uint32 diagCtrl;            /* 0x0c4 */
 113     uint32 diagStat;            /* 0x0c8 */
 114     uint32 diagMask;            /* 0x0cc */
 115     uint32 diagRslt;            /* 0x0d0 */
 116     uint32 diagCmp;             /* 0x0d4 */
 117     uint32 diagCapt;            /* 0x0d8 */
 118     uint32 diagCnt;             /* 0x0dc */
 119     uint32 diagEdgeCnt;         /* 0x0e0 */
 120     uint32 reserved5[4];            /* 0x0e4 */
 121     uint32 smisc_bus_config;    /* 0x0f4 */
 122     uint32 lfsr;                /* 0x0f8 */
 123     uint32 dqm_pac_lock;        /* 0x0fc */
 124     uint32 l1_irq_4ke_mask;     /* 0x100 */
 125     uint32 l1_irq_4ke_status;   /* 0x104 */
 126     uint32 l1_irq_mips_mask;    /* 0x108 */
 127     uint32 l1_irq_mips_status;  /* 0x10c */
 128     uint32 l1_irq_mips1_mask;   /* 0x110 */
 129     uint32 reserved6[3];        /* 0x114 */
 130     uint32 l2_irq_gp_mask;      /* 0x120 */
 131     uint32 l2_irq_gp_status;    /* 0x124 */
 132     uint32 l2_irq_gp_set;       /* 0x128 */
 133     uint32 reserved7;           /* 0x12c */
 134     uint32 gp_in_irq_mask;      /* 0x130 */
 135     uint32 gp_in_irq_status;    /* 0x134 */
 136     uint32 gp_in_irq_set;       /* 0x138 */
 137     uint32 gp_in_irq_sense;     /* 0x13c */
 138     uint32 gp_in;               /* 0x140 */
 139     uint32 gp_out;              /* 0x144 */
 140 } PmcCtrlReg;
 141
 142 typedef struct PmcDmaReg {
 143         /* 0x00 */
 144         uint32 src;
 145         uint32 dest;
 146         uint32 cmdList;
 147         uint32 lenCtl;
 148         /* 0x10 */
 149         uint32 rsltSrc;
 150         uint32 rsltDest;
 151         uint32 rsltHcs;
 152         uint32 rsltLenStat;
 153 } PmcDmaReg;
 154
 155 typedef struct PmcTokenReg {
 156         /* 0x00 */
 157         uint32 bufSize;
 158         uint32 bufBase;
 159         uint32 idx2ptrIdx;
 160         uint32 idx2ptrPtr;
 161         /* 0x10 */
 162         uint32 unused[2];
 163         uint32 bufSize2;
 164 } PmcTokenReg;
 165
 166 typedef struct PmcPerfPowReg {
 167         uint32 freqScalarCtrl; /* 0x3c */
 168         uint32 freqScalarMask; /* 0x40 */
 169 } PmcPerfPowReg;
 170
 171 typedef struct PmcDQMPac {
 172     uint32 dqmPac[32];
 173 } PmcDQMPac;
 174
 175 typedef struct PmcDQMReg {
 176         uint32 cfg;                     /* 0x1c00 */
 177         uint32 _4keLowWtmkIrqMask;      /* 0x1c04 */
 178         uint32 mipsLowWtmkIrqMask;      /* 0x1c08 */
 179         uint32 lowWtmkIrqMask;          /* 0x1c0c */
 180         uint32 _4keNotEmptyIrqMask;     /* 0x1c10 */
 181         uint32 mipsNotEmptyIrqMask;     /* 0x1c14 */
 182         uint32 notEmptyIrqSts;          /* 0x1c18 */
 183         uint32 queueRst;                /* 0x1c1c */
 184         uint32 notEmptySts;             /* 0x1c20 */
 185         uint32 nextAvailMask;           /* 0x1c24 */
 186         uint32 nextAvailQueue;          /* 0x1c28 */
 187         uint32 mips1LowWtmkIrqMask;     /* 0x1c2c */
 188         uint32 mips1NotEmptyIrqMask;    /* 0x1c30 */
 189         uint32 autoSrcPidInsert;        /* 0x1c34 */
 190     uint32 timerIrqStatus;          /* 0x1c38 */
 191     uint32 timerStatus;             /* 0x1c3c */
 192     uint32 _4keTimerIrqMask;        /* 0x1c40 */
 193     uint32 mipsTimerIrqMask;        /* 0x1c44 */
 194     uint32 mips1TimerIrqMask;       /* 0x1c48 */
 195 } PmcDQMReg;
 196
 197 typedef struct PmcCntReg {
 198         uint32 cntr[10];
 199         uint32 unused[6];       /* 0x28-0x3f */
 200         uint32 cntrIrqMask;
 201         uint32 cntrIrqSts;
 202 } PmcCntReg;
 203
 204 typedef struct PmcDqmQCtrlReg {
 205         uint32 size;
 206         uint32 cfga;
 207         uint32 cfgb;
 208         uint32 cfgc;
 209 } PmcDqmQCtrlReg;
 210
 211 typedef struct PmcDqmQDataReg {
 212         uint32 word[4];
 213 } PmcDqmQDataReg;
 214
 215 typedef struct PmcDqmQMibReg {
 216         uint32 qNumFull[32];
 217         uint32 qNumEmpty[32];
 218         uint32 qNumPushed[32];
 219 } PmcDqmQMibReg;
 220
 221 typedef struct SSBMaster {
 222     uint32 ssbmControl;     /* 0x0060 */
 223     uint32 ssbmWrData;      /* 0x0064 */
 224     uint32 ssbmRdData;      /* 0x0068 */
 225     uint32 ssbmStatus;      /* 0x006c */
 226 } SSBMaster;
 227
 228 typedef struct PmmReg {
 229     uint32 memPowerCtrl;            /* 0x0000 */
 230     uint32 regSecurityConfig;       /* 0x0004 */
 231 } PmmReg;
 232
 233 typedef struct keyholeReg {
 234     uint32 ctrlSts;
 235     uint32 wrData;
 236     uint32 mutex;
 237     uint32 rdData;
 238 } keyholeReg;
 239
 240 typedef struct PmbBus {
 241     uint32 config;          /* 0x0100 */
 242     uint32 arbiter;         /* 0x0104 */
 243     uint32 timeout;         /* 0x0108 */
 244     uint32 unused1;         /* 0x010c */
 245     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 246     uint32 unused2[44];     /* 0x0150-0x01ff */
 247     uint32 map[64];         /* 0x0200-0x02ff */
 248 }PmbBus;
 249
 250 typedef struct  CoreCtrl {
 251     uint32  coreEnable;         /* 0x0400 */
 252     uint32  autoresetControl;   /* 0x0404 */
 253     uint32  coreIdle;           /* 0x0408 */
 254     uint32  coreResetCause;     /* 0x040c */
 255     uint32  memPwrDownCtrl0;    /* 0x0410 */
 256     uint32  memPwrDownSts0;     /* 0x0414 */
 257     uint32  memPwrDownCtrl1;    /* 0x0418 */
 258     uint32  memPwrDownSts1;     /* 0x041c */
 259     uint32  sysFlg0Status;      /* 0x0420 */
 260     uint32  sysFlg0Set;         /* 0x0424 */
 261     uint32  sysFlg0Clear;       /* 0x0428 */
 262     uint32  unused1;            /* 0x042c */
 263     uint32  usrFlg0Status;      /* 0x0430 */
 264     uint32  usrFlg0Set;         /* 0x0434 */
 265     uint32  usrFlg0Clear;       /* 0x0438 */
 266     uint32  unused2;            /* 0x043c */
 267     uint32  subsystemRev;       /* 0x0440 */
 268     uint32  resetVector;        /* 0x0444 */
 269 } CoreCtrl;
 270
 271 typedef struct  CoreState {
 272     uint32  sysMbx[8];          /* 0x0480 */
 273     uint32  usrMbx[8];          /* 0x04a0 */
 274     uint32  sysMtx[4];          /* 0x04c0 */
 275     uint32  usrMtx[8];          /* 0x04d0 */
 276 } CoreState;
 277
 278 typedef struct  CoreIntr {
 279     uint32  irqStatus;          /* 0x0500 */
 280     uint32  irqSet;             /* 0x0504 */
 281     uint32  irqClear;           /* 0x0508 */
 282     uint32  unused1;            /* 0x050c */
 283     uint32  srqStatus;          /* 0x0510 */
 284     uint32  srqSet;             /* 0x0514 */
 285     uint32  srqClear;           /* 0x0518 */
 286     uint32  unused2;            /* 0x051c */
 287     uint32  drqStatus;          /* 0x0520 */
 288     uint32  drqSet;             /* 0x0524 */
 289     uint32  drqClear;           /* 0x0528 */
 290     uint32  unused3;            /* 0x052c */
 291     uint32  frqStatus;          /* 0x0530 */
 292     uint32  frqSet;             /* 0x0534 */
 293     uint32  frqClear;           /* 0x0538 */
 294     uint32  unused4;            /* 0x053c */
 295     uint32  hostIrqLatched;     /* 0x0540 */
 296     uint32  hostIrqSet;         /* 0x0544 */
 297     uint32  hostIrqClear;       /* 0x0548 */
 298     uint32  hostIrqEnable;      /* 0x054c */
 299     uint32  obusFaultStatus;    /* 0x0550 */
 300     uint32  obusFaultClear;     /* 0x0554 */
 301     uint32  obusFaultAddr;      /* 0x0558 */
 302 } CoreIntr;
 303
 304 typedef struct CoreProfile {
 305     uint32  mutex;              /* 0x0580 */
 306     uint32  lastConfPcLo;       /* 0x0584 */
 307     uint32  lastConfPcHi;       /* 0x0588 */
 308     uint32  lastPcLo;           /* 0x058c */
 309     uint32  lastPcHi;           /* 0x0590 */
 310     uint32  braTargetPc0Lo;     /* 0x0594 */
 311     uint32  braTargetPc0Hi;     /* 0x0598 */
 312     uint32  braTargetPc1Lo;     /* 0x059c */
 313     uint32  braTargetPc1Hi;     /* 0x05a0 */
 314     uint32  braTargetPc2Lo;     /* 0x05a4 */
 315     uint32  braTargetPc2Hi;     /* 0x05a8 */
 316     uint32  braTargetPc3Lo;     /* 0x05ac */
 317     uint32  braTargetPc3Hi;     /* 0x05b0 */
 318     uint32  unused[3];          /* 0x05b4-0x05bf */
 319     uint32  profSampleW[4];     /* 0x05c0 */
 320 } CoreProfile;
 321
 322 typedef struct MaestroMisc {
 323     CoreCtrl coreCtrl;          /* 0x0400 */
 324     uint32   unused1[14];       /* 0x0448-0x047f */
 325     CoreState coreState;        /* 0x0480 */
 326     uint32   unused2[4];        /* 0x04f0-0x04ff */
 327     CoreIntr interrupt;         /* 0x0500 */
 328     uint32   unused3[9];        /* 0x055c-0x057f */
 329     CoreProfile profile;        /* 0x0580 */
 330 } MaestroMisc;
 331
 332 typedef struct Pmc {
 333     uint32 unused0[1030];
 334     PmcCtrlReg ctrl;                        /* 0x1018 */
 335     uint32 unused1[622];                    /* 0x1148-0x1cff */
 336     PmcDQMPac dqmPac;                   /* 0x1b00 */
 337     uint32 unused5[32];                 /* 0x1b80-0x1bff */
 338     PmcDQMReg dqm;                                  /* 0x1c00 */
 339     uint32 unused6[749];                        /* 0x1c4c-0x27ff */
 340     uint32 qStatus[32];                     /* 0x2800 */
 341     uint32 unused7[480];                    /* 0x2880-0x2fff */
 342     PmcDqmQMibReg qMib;                     /* 0x3000 */
 343     uint32 unused8[928];                    /* 0x3180-0x3fff */
 344     PmcDqmQCtrlReg dqmQCtrl[8];             /* 0x4000 */
 345     uint32 unused9[992];                /* 0x4080-0x4fff */
 346     PmcDqmQDataReg dqmQData[8];             /* 0x5000 */
 347 } Pmc;
 348 #define PMC ((volatile Pmc * const) PMC_BASE)
 349
 350 typedef struct Procmon {
 351     uint32 unused00[256];
 352     MaestroMisc maestroReg;             /* 0x00400 */
 353     uint32 unused10[32396];             /* 0x005d0-0x1ffff */
 354     PmmReg  pmm;                        /* 0x20000 */
 355     uint32 unused11[22];                /* 0x20008-0x2005f */
 356     SSBMaster ssbMasterCtrl;            /* 0x20060 */
 357     uint32 unused12[36];                /* 0x20070-0x200ff */
 358     PmbBus pmb;                         /* 0x20100 */
 359     uint32 unused13[32576];             /* 0x20300-0x3ffff */
 360     uint32 qsm[128];                    /* 0x40000-0x401ff */
 361     uint32 unused14[65408];             /* 0x40200-0x7ffff */
 362     uint32 dtcm[1024];                  /* 0x80000-0x80fff */
 363     uint32 unused15[64512];             /* 0x81000-0xbffff */
 364     uint32 itcm[4096];                  /* 0xc0000-0xc3fff */
 365 } Procmon;
 366 #define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
 367
 368 typedef struct PMSSBMasterControl {
 369         uint32 control;
 370         uint32 wr_data;
 371         uint32 rd_data;
 372 } PMSSBMasterControl;
 373
 374 typedef struct
 375 {
 376     uint32  control;
 377 #define PMC_PMBM_START                      (1 << 31)
 378 #define PMC_PMBM_TIMEOUT                    (1 << 30)
 379 #define PMC_PMBM_SLAVE_ERR                  (1 << 29)
 380 #define PMC_PMBM_BUSY                       (1 << 28)
 381 #define PMC_PMBM_BUS_SHIFT              (20)
 382 #define PMC_PMBM_Read                       (0 << 24)
 383 #define PMC_PMBM_Write                      (1 << 24)
 384     uint32  wr_data;
 385     uint32  mutex;
 386     uint32  rd_data;
 387 } PMB_keyhole_reg;
 388
 389 typedef struct PMBMaster {
 390     uint32 config;
 391 #define PMB_NUM_REGS_SHIFT (20)
 392 #define PMB_NUM_REGS_MASK  (0x3ff)
 393     uint32 arbitger;
 394     uint32 timeout;
 395     uint32 reserved;
 396     PMB_keyhole_reg keyhole[4];
 397     uint32 reserved1[44];
 398     uint32 map[64];
 399 } PMBMaster;
 400 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 401
 402
 403 typedef struct WDTimer {
 404     uint32        WatchDogDefCount;
 405     /* Write 0xff00 0x00ff to Start timer
 406      * Write 0xee00 0x00ee to Stop and re-load default count
 407      * Read from this register returns current watch dog count
 408      */
 409     uint32        WatchDogCtl;
 410
 411     /* Number of 50-MHz ticks for WD Reset pulse to last */
 412     uint32        WDResetCount;
 413
 414     uint32        SoftRst;
 415 #define SOFT_RESET              0x00000001
 416     uint32        WDAccessCtl;
 417 } WDTimer;
 418
 419 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 420
 421
 422 typedef struct BIUCFG_Access {
 423     uint32 permission;        /* 0x0 */
 424     uint32 sbox;              /* 0x4 */
 425     uint32 cpu_defeature;     /* 0x8 */
 426     uint32 dbg_security;      /* 0xc */
 427     uint32 rsvd1[32];         /* 0x10 - 0x8f */
 428     uint64 violation[2];      /* 0x90 - 0x9f */
 429     uint32 ts_access[2];      /* 0xa0 - 0xa7 */
 430     uint32 rsvd2[22];         /* 0xa8 - 0xff */
 431 }BIUCFG_Access;
 432
 433 typedef struct BIUCFG_Cluster {
 434     uint32 permission;        /* 0x0 */
 435     uint32 config;            /* 0x4 */
 436     uint32 status;            /* 0x8 */
 437     uint32 control;           /* 0xc */
 438     uint32 cpucfg;            /* 0x10 */
 439     uint32 dbgrom;            /* 0x14 */
 440     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 441     uint64 rvbar_addr[4];     /* 0x20 - 0x3f */
 442     uint32 rsvd2[48];         /* 0x40 - 0xff */
 443 }BIUCFG_Cluster;
 444
 445 typedef struct BIUCFG_Bac {
 446     uint32 bac_permission;    /* 0x00 */
 447     uint32 bac_periphbase;    /* 0x04 */
 448     uint32 rsvd[2];           /* 0x08 - 0x0f */
 449     uint32 bac_event;         /* 0x10 */
 450     uint32 rsvd_1[3];         /* 0x14 - 0x1f */
 451     uint32 bac_ccicfg;        /* 0x20 */
 452     uint32 bac_cciaddr;       /* 0x24 */
 453     uint32 rsvd_2[4];         /* 0x28 - 0x37 */
 454     uint32 bac_ccievs2;       /* 0x38 */
 455     uint32 bac_ccievs3;       /* 0x3c */
 456     uint32 bac_ccievs4;       /* 0x40 */
 457     uint32 rsvd_3[3];         /* 0x44 - 0x4f */
 458     uint32 bac_ccievm0;       /* 0x50 */
 459     uint32 bac_ccievm1;       /* 0x54 */
 460     uint32 rsvd_4[2];         /* 0x58 - 0x5f */
 461     uint32 bac_dapapbcfg;     /* 0x60 */
 462     uint32 bac_status;        /* 0x64 */
 463     uint32 rsvd_5[2];         /* 0x68 - 0x6f */
 464     uint32 cpu_therm_irq_cfg; /* 0x70 */
 465     uint32 cpu_therm_threshold_cfg; /* 0x74 */
 466     uint32 rsvd_6;            /* 0x78 */
 467     uint32 cpu_therm_temp;    /* 0x7c */
 468     uint32 rsvd_7[32];        /* 0x80 - 0xff */
 469 } BIUCFG_Bac;
 470
 471 typedef struct BIUCFG_Aux {
 472     uint32 aux_permission;    /* 0x00 */
 473     uint32 rsvd[3];           /* 0x04 - 0x0f */
 474     uint32 c0_clk_control;    /* 0x10 */
 475     uint32 c0_clk_ramp;       /* 0x14 */
 476     uint32 c0_clk_pattern;    /* 0x18 */
 477     uint32 rsvd_1;            /* 0x1c */
 478     uint32 c1_clk_control;    /* 0x20 */
 479     uint32 c1_clk_ramp;       /* 0x24 */
 480     uint32 c1_clk_pattern;    /* 0x28 */
 481     uint32 rsvd_2[53];        /* 0x2c - 0xff */
 482 } BIUCFG_Aux;
 483
 484 typedef struct BIUCFG {
 485     BIUCFG_Access access;         /* 0x0 - 0xff*/
 486     BIUCFG_Cluster cluster[2];    /* 0x100 - 0x2ff*/
 487     BIUCFG_Bac bac;               /* 0x300 - 0x3ff */
 488     uint32 anonymous[192];        /* 0x400 - 0x6ff */
 489     BIUCFG_Aux aux;               /* 0x700 - 0x7ff */
 490     uint32 anonymous_1[2560];     /* 0x800 - 0x2fff */
 491 }BIUCFG;
 492
 493 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 494
 495
 496 #endif /* __ASSEMBLER__ */
 497
 498 #ifdef __cplusplus
 499 }
 500 #endif
 501
 502 #endif
 503