plat/bcm/include/bcm963xx/6756_map_part.h

   1 /*
   2 <:copyright-BRCM:2020:DUAL/GPL:standard
   3
   4    Copyright (c) 2020 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22
  23 */
  24
  25 #ifndef __BCM6756_MAP_PART_H
  26 #define __BCM6756_MAP_PART_H
  27
  28 #ifdef __cplusplus
  29 extern "C" {
  30 #endif
  31
  32 #include "bcmtypes.h"
  33
  34 #define CHIP_FAMILY_ID_HEX          0x6756
  35
  36 #define MEMC_PHYS_BASE              0x80180000
  37 #define MEMC_SIZE                   0x24000
  38
  39 #define PMC_PHYS_BASE               0x80200000
  40 #define PMC_SIZE                    0x00200000
  41 #define PMC_OFFSET                  0x00100000
  42 #define PROC_MON_OFFSET             0x00100000
  43 #define PMB_OFFSET                  0x00120100
  44
  45 #define PERF_PHYS_BASE              0xff800000
  46 #define PERF_SIZE                   0x13000
  47 #define TIMR_OFFSET                 0x0400
  48 #define WDTIMR0_OFFSET              0x0480
  49 #define WDTIMR1_OFFSET              0x04c0
  50
  51 #define BIU_PHYS_BASE               0x81000000
  52 #define BIUCFG_PHYS_BASE            0x81060000
  53 #define BIUCFG_SIZE                 0x3000
  54 #define BIUCFG_OFFSET               0x0000
  55
  56 #define BOOTLUT_PHYS_BASE           0xffff0000
  57 #define BOOTLUT_SIZE                0x1000
  58
  59 #define GIC_PHYS_BASE               0x81000000
  60 #define GIC_SIZE                    0x10000
  61 #define GIC_OFFSET                  0x0000
  62 #define GICD_OFFSET                 0x1000
  63 #define GICC_OFFSET                 0x2000
  64
  65 #define PMC_BASE                    (PMC_PHYS_BASE + PMC_OFFSET)
  66 #define PROC_MON_BASE               (PMC_PHYS_BASE + PROC_MON_OFFSET)
  67 #define PMB_BASE                    (PMC_PHYS_BASE + PMB_OFFSET)
  68 #define BIUCFG_BASE                 (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  69 #define WDTIMR0_BASE                (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  70
  71
  72
  73 #ifndef __ASSEMBLER__
  74
  75 /*
  76  * Power Management Control
  77  */
  78 typedef struct PmcCtrlReg {
  79     uint32 gpTmr0Ctl;           /* 0x018 */
  80     uint32 gpTmr0Cnt;           /* 0x01c */
  81     uint32 gpTmr1Ctl;           /* 0x020 */
  82     uint32 gpTmr1Cnt;           /* 0x024 */
  83     uint32 hostMboxIn;          /* 0x028 */
  84     uint32 hostMboxOut;         /* 0x02c */
  85     uint32 reserved[4];         /* 0x030 */
  86     uint32 dmaCtrl;             /* 0x040 */
  87     uint32 dmaStatus;           /* 0x044 */
  88     uint32 dma0_3FifoStatus;    /* 0x048 */
  89     uint32 reserved1[4];        /* 0x04c */
  90     uint32 diagControl;         /* 0x05c */
  91     uint32 diagHigh;            /* 0x060 */
  92     uint32 diagLow;             /* 0x064 */
  93     uint32 reserved8;           /* 0x068 */
  94     uint32 addr1WndwMask;       /* 0x06c */
  95     uint32 addr1WndwBaseIn;     /* 0x070 */
  96     uint32 addr1WndwBaseOut;    /* 0x074 */
  97     uint32 addr2WndwMask;       /* 0x078 */
  98     uint32 addr2WndwBaseIn;     /* 0x07c */
  99     uint32 addr2WndwBaseOut;    /* 0x080 */
 100     uint32 scratch;             /* 0x084 */
 101     uint32 reserved9;           /* 0x088 */
 102     uint32 softResets;          /* 0x08c */
 103     uint32 reserved2;           /* 0x090 */
 104     uint32 m4keCoreStatus;      /* 0x094 */
 105     uint32 reserved3;           /* 0x098 */
 106     uint32 ubSlaveTimeout;      /* 0x09c */
 107     uint32 diagEn;              /* 0x0a0 */
 108     uint32 devTimeout;          /* 0x0a4 */
 109     uint32 ubusErrorOutMask;    /* 0x0a8 */
 110     uint32 diagCaptStopMask;    /* 0x0ac */
 111     uint32 revId;               /* 0x0b0 */
 112     uint32 reserved4[4];        /* 0x0b4 */
 113     uint32 diagCtrl;            /* 0x0c4 */
 114     uint32 diagStat;            /* 0x0c8 */
 115     uint32 diagMask;            /* 0x0cc */
 116     uint32 diagRslt;            /* 0x0d0 */
 117     uint32 diagCmp;             /* 0x0d4 */
 118     uint32 diagCapt;            /* 0x0d8 */
 119     uint32 diagCnt;             /* 0x0dc */
 120     uint32 diagEdgeCnt;         /* 0x0e0 */
 121     uint32 reserved5[4];            /* 0x0e4 */
 122     uint32 smisc_bus_config;    /* 0x0f4 */
 123     uint32 lfsr;                /* 0x0f8 */
 124     uint32 dqm_pac_lock;        /* 0x0fc */
 125     uint32 l1_irq_4ke_mask;     /* 0x100 */
 126     uint32 l1_irq_4ke_status;   /* 0x104 */
 127     uint32 l1_irq_mips_mask;    /* 0x108 */
 128     uint32 l1_irq_mips_status;  /* 0x10c */
 129     uint32 l1_irq_mips1_mask;   /* 0x110 */
 130     uint32 reserved6[3];        /* 0x114 */
 131     uint32 l2_irq_gp_mask;      /* 0x120 */
 132     uint32 l2_irq_gp_status;    /* 0x124 */
 133     uint32 l2_irq_gp_set;       /* 0x128 */
 134     uint32 reserved7;           /* 0x12c */
 135     uint32 gp_in_irq_mask;      /* 0x130 */
 136     uint32 gp_in_irq_status;    /* 0x134 */
 137     uint32 gp_in_irq_set;       /* 0x138 */
 138     uint32 gp_in_irq_sense;     /* 0x13c */
 139     uint32 gp_in;               /* 0x140 */
 140     uint32 gp_out;              /* 0x144 */
 141 } PmcCtrlReg;
 142
 143 typedef struct PmcDmaReg {
 144         /* 0x00 */
 145         uint32 src;
 146         uint32 dest;
 147         uint32 cmdList;
 148         uint32 lenCtl;
 149         /* 0x10 */
 150         uint32 rsltSrc;
 151         uint32 rsltDest;
 152         uint32 rsltHcs;
 153         uint32 rsltLenStat;
 154 } PmcDmaReg;
 155
 156 typedef struct PmcTokenReg {
 157         /* 0x00 */
 158         uint32 bufSize;
 159         uint32 bufBase;
 160         uint32 idx2ptrIdx;
 161         uint32 idx2ptrPtr;
 162         /* 0x10 */
 163         uint32 unused[2];
 164         uint32 bufSize2;
 165 } PmcTokenReg;
 166
 167 typedef struct PmcPerfPowReg {
 168         uint32 freqScalarCtrl; /* 0x3c */
 169         uint32 freqScalarMask; /* 0x40 */
 170 } PmcPerfPowReg;
 171
 172 typedef struct PmcDQMPac {
 173     uint32 dqmPac[32];
 174 } PmcDQMPac;
 175
 176 typedef struct PmcDQMReg {
 177         uint32 cfg;                     /* 0x1c00 */
 178         uint32 _4keLowWtmkIrqMask;      /* 0x1c04 */
 179         uint32 mipsLowWtmkIrqMask;      /* 0x1c08 */
 180         uint32 lowWtmkIrqMask;          /* 0x1c0c */
 181         uint32 _4keNotEmptyIrqMask;     /* 0x1c10 */
 182         uint32 mipsNotEmptyIrqMask;     /* 0x1c14 */
 183         uint32 notEmptyIrqSts;          /* 0x1c18 */
 184         uint32 queueRst;                /* 0x1c1c */
 185         uint32 notEmptySts;             /* 0x1c20 */
 186         uint32 nextAvailMask;           /* 0x1c24 */
 187         uint32 nextAvailQueue;          /* 0x1c28 */
 188         uint32 mips1LowWtmkIrqMask;     /* 0x1c2c */
 189         uint32 mips1NotEmptyIrqMask;    /* 0x1c30 */
 190         uint32 autoSrcPidInsert;        /* 0x1c34 */
 191     uint32 timerIrqStatus;          /* 0x1c38 */
 192     uint32 timerStatus;             /* 0x1c3c */
 193     uint32 _4keTimerIrqMask;        /* 0x1c40 */
 194     uint32 mipsTimerIrqMask;        /* 0x1c44 */
 195     uint32 mips1TimerIrqMask;       /* 0x1c48 */
 196 } PmcDQMReg;
 197
 198 typedef struct PmcCntReg {
 199         uint32 cntr[10];
 200         uint32 unused[6];           /* 0x28-0x3f */
 201         uint32 cntrIrqMask;
 202         uint32 cntrIrqSts;
 203 } PmcCntReg;
 204
 205 typedef struct PmcDqmQCtrlReg {
 206         uint32 size;
 207         uint32 cfga;
 208         uint32 cfgb;
 209         uint32 cfgc;
 210 } PmcDqmQCtrlReg;
 211
 212 typedef struct PmcDqmQDataReg {
 213         uint32 word[4];
 214 } PmcDqmQDataReg;
 215
 216 typedef struct PmcDqmQMibReg {
 217         uint32 qNumFull[32];
 218         uint32 qNumEmpty[32];
 219         uint32 qNumPushed[32];
 220 } PmcDqmQMibReg;
 221
 222 typedef struct SSBMaster {
 223     uint32 ssbmControl;     /* 0x0060 */
 224     uint32 ssbmWrData;      /* 0x0064 */
 225     uint32 ssbmRdData;      /* 0x0068 */
 226     uint32 ssbmStatus;      /* 0x006c */
 227 } SSBMaster;
 228
 229 typedef struct PmmReg {
 230     uint32 memPowerCtrl;            /* 0x0000 */
 231     uint32 regSecurityConfig;       /* 0x0004 */
 232 } PmmReg;
 233
 234 typedef struct keyholeReg {
 235     uint32 ctrlSts;
 236     uint32 wrData;
 237     uint32 mutex;
 238     uint32 rdData;
 239 } keyholeReg;
 240
 241 typedef struct PmbBus {
 242     uint32 config;          /* 0x0100 */
 243     uint32 arbiter;         /* 0x0104 */
 244     uint32 timeout;         /* 0x0108 */
 245     uint32 unused1;         /* 0x010c */
 246     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 247     uint32 unused2[44];     /* 0x0150-0x01ff */
 248     uint32 map[64];         /* 0x0200-0x02ff */
 249 }PmbBus;
 250
 251 typedef struct  CoreCtrl {
 252     uint32  coreEnable;         /* 0x0400 */
 253     uint32  autoresetControl;   /* 0x0404 */
 254     uint32  coreIdle;           /* 0x0408 */
 255     uint32  coreResetCause;     /* 0x040c */
 256     uint32  memPwrDownCtrl0;    /* 0x0410 */
 257     uint32  memPwrDownSts0;     /* 0x0414 */
 258     uint32  memPwrDownCtrl1;    /* 0x0418 */
 259     uint32  memPwrDownSts1;     /* 0x041c */
 260     uint32  sysFlg0Status;      /* 0x0420 */
 261     uint32  sysFlg0Set;         /* 0x0424 */
 262     uint32  sysFlg0Clear;       /* 0x0428 */
 263     uint32  unused1;            /* 0x042c */
 264     uint32  usrFlg0Status;      /* 0x0430 */
 265     uint32  usrFlg0Set;         /* 0x0434 */
 266     uint32  usrFlg0Clear;       /* 0x0438 */
 267     uint32  unused2;            /* 0x043c */
 268     uint32  subsystemRev;       /* 0x0440 */
 269     uint32  resetVector;        /* 0x0444 */
 270 } CoreCtrl;
 271
 272 typedef struct  CoreState {
 273     uint32  sysMbx[8];          /* 0x0480 */
 274     uint32  usrMbx[8];          /* 0x04a0 */
 275     uint32  sysMtx[4];          /* 0x04c0 */
 276     uint32  usrMtx[8];          /* 0x04d0 */
 277 } CoreState;
 278
 279 typedef struct  CoreIntr {
 280     uint32  irqStatus;          /* 0x0500 */
 281     uint32  irqSet;             /* 0x0504 */
 282     uint32  irqClear;           /* 0x0508 */
 283     uint32  unused1;            /* 0x050c */
 284     uint32  srqStatus;          /* 0x0510 */
 285     uint32  srqSet;             /* 0x0514 */
 286     uint32  srqClear;           /* 0x0518 */
 287     uint32  unused2;            /* 0x051c */
 288     uint32  drqStatus;          /* 0x0520 */
 289     uint32  drqSet;             /* 0x0524 */
 290     uint32  drqClear;           /* 0x0528 */
 291     uint32  unused3;            /* 0x052c */
 292     uint32  frqStatus;          /* 0x0530 */
 293     uint32  frqSet;             /* 0x0534 */
 294     uint32  frqClear;           /* 0x0538 */
 295     uint32  unused4;            /* 0x053c */
 296     uint32  hostIrqLatched;     /* 0x0540 */
 297     uint32  hostIrqSet;         /* 0x0544 */
 298     uint32  hostIrqClear;       /* 0x0548 */
 299     uint32  hostIrqEnable;      /* 0x054c */
 300     uint32  obusFaultStatus;    /* 0x0550 */
 301     uint32  obusFaultClear;     /* 0x0554 */
 302     uint32  obusFaultAddr;      /* 0x0558 */
 303 } CoreIntr;
 304
 305 typedef struct CoreProfile {
 306     uint32  mutex;              /* 0x0580 */
 307     uint32  lastConfPcLo;       /* 0x0584 */
 308     uint32  lastConfPcHi;       /* 0x0588 */
 309     uint32  lastPcLo;           /* 0x058c */
 310     uint32  lastPcHi;           /* 0x0590 */
 311     uint32  braTargetPc0Lo;     /* 0x0594 */
 312     uint32  braTargetPc0Hi;     /* 0x0598 */
 313     uint32  braTargetPc1Lo;     /* 0x059c */
 314     uint32  braTargetPc1Hi;     /* 0x05a0 */
 315     uint32  braTargetPc2Lo;     /* 0x05a4 */
 316     uint32  braTargetPc2Hi;     /* 0x05a8 */
 317     uint32  braTargetPc3Lo;     /* 0x05ac */
 318     uint32  braTargetPc3Hi;     /* 0x05b0 */
 319     uint32  unused[3];          /* 0x05b4-0x05bf */
 320     uint32  profSampleW[4];     /* 0x05c0 */
 321 } CoreProfile;
 322
 323 typedef struct MaestroMisc {
 324     CoreCtrl coreCtrl;          /* 0x0400 */
 325     uint32   unused1[14];       /* 0x0448-0x047f */
 326     CoreState coreState;        /* 0x0480 */
 327     uint32   unused2[4];        /* 0x04f0-0x04ff */
 328     CoreIntr interrupt;         /* 0x0500 */
 329     uint32   unused3[9];        /* 0x055c-0x057f */
 330     CoreProfile profile;        /* 0x0580 */
 331 } MaestroMisc;
 332
 333 typedef struct Pmc {
 334     uint32 unused0[1030];
 335     PmcCtrlReg ctrl;            /* 0x1018 */
 336     uint32 unused1[622];        /* 0x1148-0x1cff */
 337     PmcDQMPac dqmPac;           /* 0x1b00 */
 338     uint32 unused5[32];         /* 0x1b80-0x1bff */
 339     PmcDQMReg dqm;              /* 0x1c00 */
 340     uint32 unused6[749];        /* 0x1c4c-0x27ff */
 341     uint32 qStatus[32];         /* 0x2800 */
 342     uint32 unused7[480];        /* 0x2880-0x2fff */
 343     PmcDqmQMibReg qMib;         /* 0x3000 */
 344     uint32 unused8[928];        /* 0x3180-0x3fff */
 345     PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */
 346     uint32 unused9[992];        /* 0x4080-0x4fff */
 347     PmcDqmQDataReg dqmQData[8]; /* 0x5000 */
 348 } Pmc;
 349
 350 #define PMC ((volatile Pmc * const) PMC_BASE)
 351 typedef struct Procmon {
 352     uint32 unused00[256];
 353     MaestroMisc maestroReg;     /* 0x00400 */
 354     uint32 unused10[32396];     /* 0x005d0-0x1ffff */
 355     PmmReg  pmm;                /* 0x20000 */
 356     uint32 unused11[22];        /* 0x20008-0x2005f */
 357     SSBMaster ssbMasterCtrl;    /* 0x20060 */
 358     uint32 unused12[36];        /* 0x20070-0x200ff */
 359     PmbBus pmb;                 /* 0x20100 */
 360     uint32 unused13[32576];     /* 0x20300-0x3ffff */
 361     uint32 qsm[128];            /* 0x40000-0x401ff */
 362     uint32 unused14[65408];     /* 0x40200-0x7ffff */
 363     uint32 dtcm[1024];          /* 0x80000-0x80fff */
 364 } Procmon;
 365 #define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
 366
 367 typedef struct PMSSBMasterControl {
 368     uint32 control;
 369     uint32 wr_data;
 370     uint32 rd_data;
 371 } PMSSBMasterControl;
 372
 373 typedef struct
 374 {
 375     uint32  control;
 376 #define PMC_PMBM_START                (1 << 31)
 377 #define PMC_PMBM_TIMEOUT              (1 << 30)
 378 #define PMC_PMBM_SLAVE_ERR            (1 << 29)
 379 #define PMC_PMBM_BUSY                 (1 << 28)
 380 #define PMC_PMBM_BUS_SHIFT            (20)
 381 #define PMC_PMBM_Read                 (0 << 24)
 382 #define PMC_PMBM_Write                (1 << 24)
 383     uint32  wr_data;
 384     uint32  mutex;
 385     uint32  rd_data;
 386 } PMB_keyhole_reg;
 387
 388 typedef struct PMBMaster {
 389     uint32 config;
 390 #define PMB_NUM_REGS_SHIFT (20)
 391 #define PMB_NUM_REGS_MASK  (0x3ff)
 392     uint32 arbitger;
 393     uint32 timeout;
 394     uint32 reserved;
 395     PMB_keyhole_reg keyhole[4];
 396     uint32 reserved1[44];
 397     uint32 map[64];
 398 } PMBMaster;
 399 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 400
 401 typedef struct WDTimer {
 402     uint32        WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer
 403      * Write 0xee00 0x00ee to Stop and re-load default count
 404      * Read from this register returns current watch dog count
 405      */
 406     uint32        WatchDogCtl;
 407
 408     /* Number of 50-MHz ticks for WD Reset pulse to last */
 409     uint32        WDResetCount;
 410
 411 #define SOFT_RESET              0x00000001
 412     uint32        WDTimerCtl;
 413
 414     uint32        WDAccessCtl;
 415 } WDTimer;
 416
 417 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 418
 419 typedef struct BIUCFG_Access {
 420     uint32_t permission;       /* 0x0 */
 421     uint32_t sbox;             /* 0x4 */
 422     uint32_t cpu_defeature;    /* 0x8 */
 423     uint32_t dbg_security;     /* 0xc */
 424     uint32_t rsvd1[32];        /* 0x10 - 0x8f */
 425     uint64_t violation[2];     /* 0x90 - 0x9f */
 426     uint32_t ts_access[2];     /* 0xa0 - 0xa7 */
 427     uint32_t rsvd2[22];        /* 0xa8 - 0xff */
 428 } BIUCFG_Access;
 429
 430 typedef struct BIUCFG_Cluster {
 431     uint32_t permission;       /* 0x0 */
 432     uint32_t config;           /* 0x4 */
 433     uint32_t status;           /* 0x8 */
 434     uint32_t control;          /* 0xc */
 435     uint32_t cpucfg;           /* 0x10 */
 436     uint32_t dbgrom;           /* 0x14 */
 437     uint32_t rsvd1[2];         /* 0x18 - 0x1f */
 438     uint32_t rvbar_addr[4];    /* 0x20 - 0x2f */
 439     uint32_t rsvd2[52];        /* 0x30 - 0xff */
 440 } BIUCFG_Cluster;
 441
 442 typedef struct BIUCFG_AuxClkCtrl {
 443     uint32_t clk_control;      /* 0x0 */
 444     uint32_t clk_ramp;         /* 0x4 */
 445     uint32_t clk_pattern;      /* 0x8 */
 446     uint32_t rsvd;             /* 0xC */
 447 } BIUCFG_AuxClkCtrl;
 448
 449 typedef struct BIUCFGux {
 450     uint32_t permission;       /* 0 */
 451     uint32_t rsvd1[3];         /* 0x04 - 0x0c */
 452     BIUCFG_AuxClkCtrl cluster_clkctrl[2];/* 0x10 - 0x2c */
 453     uint32_t rsvd2[52];        /* 0x30 - 0xFF */
 454 } BIUCFG_Aux;
 455
 456 typedef struct BIUCFG_Bac {
 457     uint32_t bac_permission;   /* 0x00 */
 458     uint32_t bac_periphbase;   /* 0x04 */
 459     uint32_t rsvd[2];          /* 0x08 - 0x0f */
 460     uint32_t bac_event;        /* 0x10 */
 461     uint32_t rsvd_1[3];        /* 0x14 - 0x1f */
 462     uint32_t bac_ccicfg;       /* 0x20 */
 463     uint32_t bac_cciaddr;      /* 0x24 */
 464     uint32_t rsvd_2[4];        /* 0x28 - 0x37 */
 465     uint32_t bac_ccievs2;      /* 0x38 */
 466     uint32_t bac_ccievs3;      /* 0x3c */
 467     uint32_t bac_ccievs4;      /* 0x40 */
 468     uint32_t rsvd_3[3];        /* 0x44 - 0x4f */
 469     uint32_t bac_ccievm0;      /* 0x50 */
 470     uint32_t bac_ccievm1;      /* 0x54 */
 471     uint32_t rsvd_4[2];        /* 0x58 - 0x5f */
 472     uint32_t bac_dapapbcfg;    /* 0x60 */
 473     uint32_t bac_status;       /* 0x64 */
 474     uint32_t rsvd_5[2];        /* 0x68 - 0x6f */
 475     uint32_t cpu_therm_irq_cfg;/* 0x70 */
 476     uint32_t cpu_therm_threshold_cfg; /* 0x74 */
 477     uint32_t rsvd_6;           /* 0x78 */
 478     uint32_t cpu_therm_temp;   /* 0x7c */
 479     uint32_t rsvd_7[32];       /* 0x80 - 0xff */
 480 } BIUCFG_Bac;
 481
 482 typedef struct BIUCFG {
 483     BIUCFG_Access access;      /* 0x0 - 0xff */
 484     BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff */
 485     BIUCFG_Bac bac;            /* 0x300 - 0x3ff */
 486     uint32_t rsvd1[192];       /* 0x400 - 0x6ff */
 487     BIUCFG_Aux aux;            /* 0x700 - 0x7ff */
 488     uint32_t rsrvd2[512];      /* 0x800 - 0xfff */
 489     uint32_t TSO_CNTCR;        /* 0x1000 */
 490     uint32_t rsvd2[2047];      /* 0x1004 - 0x2fff */
 491 } BIUCFG;
 492
 493 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 494
 495 #endif /* __ASSEMBLER__ */
 496
 497 #ifdef __cplusplus
 498 }
 499 #endif
 500
 501 #endif
 502
 503
 504