plat/bcm/include/bcm963xx/63146_map_part.h

   1 /*
   2 <:copyright-BRCM:2019:DUAL/GPL:standard
   3
   4    Copyright (c) 2019 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef __BCM63146_MAP_PART_H
  25 #define __BCM63146_MAP_PART_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #include "bcmtypes.h"
  32
  33
  34 #define MEMC_PHYS_BASE          0x80040000  /* MC2 TOP */
  35 #define MEMC_SIZE               0x00040000
  36
  37 #define PMC_PHYS_BASE           0xffa00000
  38 #define PMC_SIZE                0x00200000
  39 #define PMC_OFFSET              0x00100000
  40 #define PROC_MON_OFFSET         0x00100000
  41 #define PMB_OFFSET              0x00120100
  42
  43 #define PERF_PHYS_BASE          0xff800000
  44 #define PERF_SIZE               0x3000
  45 #define TIMR_OFFSET             0x0400   /* 64 bit timer registers */
  46 #define WDTIMR0_OFFSET          0x0480
  47 #define WDTIMR1_OFFSET          0x04c0
  48
  49 #define BIUCFG_PHYS_BASE        0x81060000
  50 #define BIUCFG_SIZE             0x3000
  51 #define BIUCFG_OFFSET           0x0000
  52
  53 #define GIC_PHYS_BASE           0x81000000
  54 #define GIC_SIZE                0x10000
  55 #define GIC_OFFSET              0x0000
  56 #define GICD_OFFSET             0x1000
  57 #define GICC_OFFSET             0x2000
  58
  59 #define PMC_BASE                (PMC_PHYS_BASE + PMC_OFFSET)
  60 #define PROC_MON_BASE           (PMC_PHYS_BASE + PROC_MON_OFFSET)
  61 #define PMB_BASE                (PMC_PHYS_BASE + PMB_OFFSET)
  62 #define TIMR_BASE               (PERF_PHYS_BASE + TIMR_OFFSET
  63 #define WDTIMR0_BASE            (PERF_PHYS_BASE + WDTIMR0_OFFSET)
  64 #define BIUCFG_BASE             (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
  65
  66 #ifndef __ASSEMBLER__
  67
  68 /*
  69  * Power Management Control
  70  */
  71 typedef struct PmcCtrlReg {
  72     uint32 gpTmr0Ctl;           /* 0x018 */
  73     uint32 gpTmr0Cnt;           /* 0x01c */
  74     uint32 gpTmr1Ctl;           /* 0x020 */
  75     uint32 gpTmr1Cnt;           /* 0x024 */
  76     uint32 hostMboxIn;          /* 0x028 */
  77     uint32 hostMboxOut;         /* 0x02c */
  78     uint32 reserved[4];         /* 0x030 */
  79     uint32 dmaCtrl;             /* 0x040 */
  80     uint32 dmaStatus;           /* 0x044 */
  81     uint32 dma0_3FifoStatus;    /* 0x048 */
  82     uint32 reserved1[4];            /* 0x04c */
  83     uint32 diagControl;         /* 0x05c */
  84     uint32 diagHigh;            /* 0x060 */
  85     uint32 diagLow;             /* 0x064 */
  86     uint32 reserved8;           /* 0x068 */
  87     uint32 addr1WndwMask;       /* 0x06c */
  88     uint32 addr1WndwBaseIn;     /* 0x070 */
  89     uint32 addr1WndwBaseOut;    /* 0x074 */
  90     uint32 addr2WndwMask;       /* 0x078 */
  91     uint32 addr2WndwBaseIn;     /* 0x07c */
  92     uint32 addr2WndwBaseOut;    /* 0x080 */
  93     uint32 scratch;             /* 0x084 */
  94     uint32 reserved9;           /* 0x088 */
  95     uint32 softResets;          /* 0x08c */
  96     uint32 reserved2;           /* 0x090 */
  97     uint32 m4keCoreStatus;      /* 0x094 */
  98     uint32 reserved3;           /* 0x098 */
  99     uint32 ubSlaveTimeout;      /* 0x09c */
 100     uint32 diagEn;              /* 0x0a0 */
 101     uint32 devTimeout;          /* 0x0a4 */
 102     uint32 ubusErrorOutMask;    /* 0x0a8 */
 103     uint32 diagCaptStopMask;    /* 0x0ac */
 104     uint32 revId;               /* 0x0b0 */
 105     uint32 reserved4[4];        /* 0x0b4 */
 106     uint32 diagCtrl;            /* 0x0c4 */
 107     uint32 diagStat;            /* 0x0c8 */
 108     uint32 diagMask;            /* 0x0cc */
 109     uint32 diagRslt;            /* 0x0d0 */
 110     uint32 diagCmp;             /* 0x0d4 */
 111     uint32 diagCapt;            /* 0x0d8 */
 112     uint32 diagCnt;             /* 0x0dc */
 113     uint32 diagEdgeCnt;         /* 0x0e0 */
 114     uint32 reserved5[4];            /* 0x0e4 */
 115     uint32 smisc_bus_config;    /* 0x0f4 */
 116     uint32 lfsr;                /* 0x0f8 */
 117     uint32 dqm_pac_lock;        /* 0x0fc */
 118     uint32 l1_irq_4ke_mask;     /* 0x100 */
 119     uint32 l1_irq_4ke_status;   /* 0x104 */
 120     uint32 l1_irq_mips_mask;    /* 0x108 */
 121     uint32 l1_irq_mips_status;  /* 0x10c */
 122     uint32 l1_irq_mips1_mask;   /* 0x110 */
 123     uint32 reserved6[3];        /* 0x114 */
 124     uint32 l2_irq_gp_mask;      /* 0x120 */
 125     uint32 l2_irq_gp_status;    /* 0x124 */
 126     uint32 l2_irq_gp_set;       /* 0x128 */
 127     uint32 reserved7;           /* 0x12c */
 128     uint32 gp_in_irq_mask;      /* 0x130 */
 129     uint32 gp_in_irq_status;    /* 0x134 */
 130     uint32 gp_in_irq_set;       /* 0x138 */
 131     uint32 gp_in_irq_sense;     /* 0x13c */
 132     uint32 gp_in;               /* 0x140 */
 133     uint32 gp_out;              /* 0x144 */
 134 } PmcCtrlReg;
 135
 136 typedef struct PmcDmaReg {
 137         /* 0x00 */
 138         uint32 src;
 139         uint32 dest;
 140         uint32 cmdList;
 141         uint32 lenCtl;
 142         /* 0x10 */
 143         uint32 rsltSrc;
 144         uint32 rsltDest;
 145         uint32 rsltHcs;
 146         uint32 rsltLenStat;
 147 } PmcDmaReg;
 148
 149 typedef struct PmcTokenReg {
 150         /* 0x00 */
 151         uint32 bufSize;
 152         uint32 bufBase;
 153         uint32 idx2ptrIdx;
 154         uint32 idx2ptrPtr;
 155         /* 0x10 */
 156         uint32 unused[2];
 157         uint32 bufSize2;
 158 } PmcTokenReg;
 159
 160 typedef struct PmcPerfPowReg {
 161         uint32 freqScalarCtrl; /* 0x3c */
 162         uint32 freqScalarMask; /* 0x40 */
 163 } PmcPerfPowReg;
 164
 165 typedef struct PmcDQMPac {
 166     uint32 dqmPac[32];
 167 } PmcDQMPac;
 168
 169 typedef struct PmcDQMReg {
 170         uint32 cfg;                     /* 0x1c00 */
 171         uint32 _4keLowWtmkIrqMask;      /* 0x1c04 */
 172         uint32 mipsLowWtmkIrqMask;      /* 0x1c08 */
 173         uint32 lowWtmkIrqMask;          /* 0x1c0c */
 174         uint32 _4keNotEmptyIrqMask;     /* 0x1c10 */
 175         uint32 mipsNotEmptyIrqMask;     /* 0x1c14 */
 176         uint32 notEmptyIrqSts;          /* 0x1c18 */
 177         uint32 queueRst;                /* 0x1c1c */
 178         uint32 notEmptySts;             /* 0x1c20 */
 179         uint32 nextAvailMask;           /* 0x1c24 */
 180         uint32 nextAvailQueue;          /* 0x1c28 */
 181         uint32 mips1LowWtmkIrqMask;     /* 0x1c2c */
 182         uint32 mips1NotEmptyIrqMask;    /* 0x1c30 */
 183         uint32 autoSrcPidInsert;        /* 0x1c34 */
 184     uint32 timerIrqStatus;          /* 0x1c38 */
 185     uint32 timerStatus;             /* 0x1c3c */
 186     uint32 _4keTimerIrqMask;        /* 0x1c40 */
 187     uint32 mipsTimerIrqMask;        /* 0x1c44 */
 188     uint32 mips1TimerIrqMask;       /* 0x1c48 */
 189 } PmcDQMReg;
 190
 191 typedef struct PmcCntReg {
 192         uint32 cntr[10];
 193         uint32 unused[6];       /* 0x28-0x3f */
 194         uint32 cntrIrqMask;
 195         uint32 cntrIrqSts;
 196 } PmcCntReg;
 197
 198 typedef struct PmcDqmQCtrlReg {
 199         uint32 size;
 200         uint32 cfga;
 201         uint32 cfgb;
 202         uint32 cfgc;
 203 } PmcDqmQCtrlReg;
 204
 205 typedef struct PmcDqmQDataReg {
 206         uint32 word[4];
 207 } PmcDqmQDataReg;
 208
 209 typedef struct PmcDqmQMibReg {
 210         uint32 qNumFull[32];
 211         uint32 qNumEmpty[32];
 212         uint32 qNumPushed[32];
 213 } PmcDqmQMibReg;
 214
 215 typedef struct SSBMaster {
 216     uint32 ssbmControl;     /* 0x0060 */
 217     uint32 ssbmWrData;      /* 0x0064 */
 218     uint32 ssbmRdData;      /* 0x0068 */
 219     uint32 ssbmStatus;      /* 0x006c */
 220 } SSBMaster;
 221
 222 typedef struct PmmReg {
 223     uint32 memPowerCtrl;            /* 0x0000 */
 224     uint32 regSecurityConfig;       /* 0x0004 */
 225 } PmmReg;
 226
 227 typedef struct keyholeReg {
 228     uint32 ctrlSts;
 229     uint32 wrData;
 230     uint32 mutex;
 231     uint32 rdData;
 232 } keyholeReg;
 233
 234 typedef struct PmbBus {
 235     uint32 config;          /* 0x0100 */
 236     uint32 arbiter;         /* 0x0104 */
 237     uint32 timeout;         /* 0x0108 */
 238     uint32 unused1;         /* 0x010c */
 239     keyholeReg keyhole[4];  /* 0x0110-0x014f */
 240     uint32 unused2[44];     /* 0x0150-0x01ff */
 241     uint32 map[64];         /* 0x0200-0x02ff */
 242 }PmbBus;
 243
 244 typedef struct  CoreCtrl {
 245     uint32  coreEnable;         /* 0x0400 */
 246     uint32  autoresetControl;   /* 0x0404 */
 247     uint32  coreIdle;           /* 0x0408 */
 248     uint32  coreResetCause;     /* 0x040c */
 249     uint32  memPwrDownCtrl0;    /* 0x0410 */
 250     uint32  memPwrDownSts0;     /* 0x0414 */
 251     uint32  memPwrDownCtrl1;    /* 0x0418 */
 252     uint32  memPwrDownSts1;     /* 0x041c */
 253     uint32  sysFlg0Status;      /* 0x0420 */
 254     uint32  sysFlg0Set;         /* 0x0424 */
 255     uint32  sysFlg0Clear;       /* 0x0428 */
 256     uint32  unused1;            /* 0x042c */
 257     uint32  usrFlg0Status;      /* 0x0430 */
 258     uint32  usrFlg0Set;         /* 0x0434 */
 259     uint32  usrFlg0Clear;       /* 0x0438 */
 260     uint32  unused2;            /* 0x043c */
 261     uint32  subsystemRev;       /* 0x0440 */
 262     uint32  resetVector;        /* 0x0444 */
 263 } CoreCtrl;
 264
 265 typedef struct  CoreState {
 266     uint32  sysMbx[8];          /* 0x0480 */
 267     uint32  usrMbx[8];          /* 0x04a0 */
 268     uint32  sysMtx[4];          /* 0x04c0 */
 269     uint32  usrMtx[8];          /* 0x04d0 */
 270 } CoreState;
 271
 272 typedef struct  CoreIntr {
 273     uint32  irqStatus;          /* 0x0500 */
 274     uint32  irqSet;             /* 0x0504 */
 275     uint32  irqClear;           /* 0x0508 */
 276     uint32  unused1;            /* 0x050c */
 277     uint32  srqStatus;          /* 0x0510 */
 278     uint32  srqSet;             /* 0x0514 */
 279     uint32  srqClear;           /* 0x0518 */
 280     uint32  unused2;            /* 0x051c */
 281     uint32  drqStatus;          /* 0x0520 */
 282     uint32  drqSet;             /* 0x0524 */
 283     uint32  drqClear;           /* 0x0528 */
 284     uint32  unused3;            /* 0x052c */
 285     uint32  frqStatus;          /* 0x0530 */
 286     uint32  frqSet;             /* 0x0534 */
 287     uint32  frqClear;           /* 0x0538 */
 288     uint32  unused4;            /* 0x053c */
 289     uint32  hostIrqLatched;     /* 0x0540 */
 290     uint32  hostIrqSet;         /* 0x0544 */
 291     uint32  hostIrqClear;       /* 0x0548 */
 292     uint32  hostIrqEnable;      /* 0x054c */
 293     uint32  obusFaultStatus;    /* 0x0550 */
 294     uint32  obusFaultClear;     /* 0x0554 */
 295     uint32  obusFaultAddr;      /* 0x0558 */
 296 } CoreIntr;
 297
 298 typedef struct CoreProfile {
 299     uint32  mutex;              /* 0x0580 */
 300     uint32  lastConfPcLo;       /* 0x0584 */
 301     uint32  lastConfPcHi;       /* 0x0588 */
 302     uint32  lastPcLo;           /* 0x058c */
 303     uint32  lastPcHi;           /* 0x0590 */
 304     uint32  braTargetPc0Lo;     /* 0x0594 */
 305     uint32  braTargetPc0Hi;     /* 0x0598 */
 306     uint32  braTargetPc1Lo;     /* 0x059c */
 307     uint32  braTargetPc1Hi;     /* 0x05a0 */
 308     uint32  braTargetPc2Lo;     /* 0x05a4 */
 309     uint32  braTargetPc2Hi;     /* 0x05a8 */
 310     uint32  braTargetPc3Lo;     /* 0x05ac */
 311     uint32  braTargetPc3Hi;     /* 0x05b0 */
 312     uint32  unused[3];          /* 0x05b4-0x05bf */
 313     uint32  profSampleW[4];     /* 0x05c0 */
 314 } CoreProfile;
 315
 316 typedef struct MaestroMisc {
 317     CoreCtrl coreCtrl;          /* 0x0400 */
 318     uint32   unused1[14];       /* 0x0448-0x047f */
 319     CoreState coreState;        /* 0x0480 */
 320     uint32   unused2[4];        /* 0x04f0-0x04ff */
 321     CoreIntr interrupt;         /* 0x0500 */
 322     uint32   unused3[9];        /* 0x055c-0x057f */
 323     CoreProfile profile;        /* 0x0580 */
 324 } MaestroMisc;
 325
 326 typedef struct Pmc {
 327     uint32 unused0[1030];
 328     PmcCtrlReg ctrl;                        /* 0x1018 */
 329     uint32 unused1[622];                    /* 0x1148-0x1cff */
 330     PmcDQMPac dqmPac;                   /* 0x1b00 */
 331     uint32 unused5[32];                 /* 0x1b80-0x1bff */
 332     PmcDQMReg dqm;                                  /* 0x1c00 */
 333     uint32 unused6[749];                        /* 0x1c4c-0x27ff */
 334     uint32 qStatus[32];                     /* 0x2800 */
 335     uint32 unused7[480];                    /* 0x2880-0x2fff */
 336     PmcDqmQMibReg qMib;                     /* 0x3000 */
 337     uint32 unused8[928];                    /* 0x3180-0x3fff */
 338     PmcDqmQCtrlReg dqmQCtrl[8];             /* 0x4000 */
 339     uint32 unused9[992];                /* 0x4080-0x4fff */
 340     PmcDqmQDataReg dqmQData[8];             /* 0x5000 */
 341 } Pmc;
 342 #define PMC ((volatile Pmc * const) PMC_BASE)
 343
 344 typedef struct Procmon {
 345     uint32 unused00[256];
 346     MaestroMisc maestroReg;             /* 0x00400 */
 347     uint32 unused10[32396];             /* 0x005d0-0x1ffff */
 348     PmmReg  pmm;                        /* 0x20000 */
 349     uint32 unused11[22];                /* 0x20008-0x2005f */
 350     SSBMaster ssbMasterCtrl;            /* 0x20060 */
 351     uint32 unused12[36];                /* 0x20070-0x200ff */
 352     PmbBus pmb;                         /* 0x20100 */
 353     uint32 unused13[32576];             /* 0x20300-0x3ffff */
 354     uint32 qsm[128];                    /* 0x40000-0x401ff */
 355     uint32 unused14[65408];             /* 0x40200-0x7ffff */
 356     uint32 dtcm[1024];                  /* 0x80000-0x80fff */
 357     uint32 unused15[64512];             /* 0x81000-0xbffff */
 358     uint32 itcm[4096];                  /* 0xc0000-0xc3fff */
 359 } Procmon;
 360 #define PROCMON ((volatile Procmon * const) PROC_MON_BASE)
 361
 362 typedef struct PMSSBMasterControl {
 363         uint32 control;
 364         uint32 wr_data;
 365         uint32 rd_data;
 366 } PMSSBMasterControl;
 367
 368 typedef struct
 369 {
 370     uint32  control;
 371 #define PMC_PMBM_START                      (1 << 31)
 372 #define PMC_PMBM_TIMEOUT                    (1 << 30)
 373 #define PMC_PMBM_SLAVE_ERR                  (1 << 29)
 374 #define PMC_PMBM_BUSY                       (1 << 28)
 375 #define PMC_PMBM_BUS_SHIFT              (20)
 376 #define PMC_PMBM_Read                       (0 << 24)
 377 #define PMC_PMBM_Write                      (1 << 24)
 378     uint32  wr_data;
 379     uint32  mutex;
 380     uint32  rd_data;
 381 } PMB_keyhole_reg;
 382
 383 typedef struct PMBMaster {
 384     uint32 config;
 385 #define PMB_NUM_REGS_SHIFT (20)
 386 #define PMB_NUM_REGS_MASK  (0x3ff)
 387     uint32 arbitger;
 388     uint32 timeout;
 389     uint32 reserved;
 390     PMB_keyhole_reg keyhole[4];
 391     uint32 reserved1[44];
 392     uint32 map[64];
 393 } PMBMaster;
 394 #define PMB ((volatile PMBMaster * const) PMB_BASE)
 395
 396
 397 /*
 398  * Timer
 399  */
 400 #define TIMER_64BIT
 401 typedef struct Timer {
 402     uint64        TimerCtl0; /* 0x00 */
 403     uint64        TimerCtl1; /* 0x08 */
 404     uint64        TimerCtl2; /* 0x10 */
 405     uint64        TimerCtl3; /* 0x18 */
 406 #define TIMERENABLE     (1ULL << 63)
 407 #define RSTCNTCLR       (1ULL << 62)
 408     uint64        TimerCnt0; /* 0x20 */
 409     uint64        TimerCnt1; /* 0x28 */
 410     uint64        TimerCnt2; /* 0x30 */
 411     uint64        TimerCnt3; /* 0x38 */
 412 #define TIMER_COUNT_MASK   0x3FFFFFFFFFFFFFFFULL
 413     uint32        TimerMask; /* 0x40 */
 414 #define TIMER0EN        0x01
 415 #define TIMER1EN        0x02
 416 #define TIMER2EN        0x04
 417 #define TIMER3EN        0x08
 418     uint32        TimerInts; /* 0x44 */
 419 #define TIMER0          0x01
 420 #define TIMER1          0x02
 421 #define TIMER2          0x04
 422 #define TIMER3          0x08
 423     uint32        ResetReason;/* 0x4c */
 424     uint32        spare[3];   /* 0x50 - 0x5b */
 425     uint32        reserved1[9]; /* 0x5c - 0x7f */
 426 } Timer;
 427
 428 #define TIMER ((volatile Timer * const) TIMR_BASE)
 429
 430
 431 typedef struct WDTimer {
 432     uint32        WatchDogDefCount;
 433     /* Write 0xff00 0x00ff to Start timer
 434      * Write 0xee00 0x00ee to Stop and re-load default count
 435      * Read from this register returns current watch dog count
 436      */
 437     uint32        WatchDogCtl;
 438
 439     /* Number of 50-MHz ticks for WD Reset pulse to last */
 440     uint32        WDResetCount;
 441
 442     uint32        SoftRst;
 443 #define SOFT_RESET              0x00000001
 444     uint32        WDAccessCtl;
 445 } WDTimer;
 446
 447 #define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE)
 448
 449 typedef struct BIUCFG_Access {
 450     uint32 permission;        /* 0x0 */
 451     uint32 sbox;              /* 0x4 */
 452     uint32 cpu_defeature;     /* 0x8 */
 453     uint32 dbg_security;      /* 0xc */
 454     uint32 rsvd1[32];         /* 0x10 - 0x8f */
 455     uint64 violation[2];      /* 0x90 - 0x9f */
 456     uint32 ts_access[2];      /* 0xa0 - 0xa7 */
 457     uint32 rsvd2[22];         /* 0xa8 - 0xff */
 458 }BIUCFG_Access;
 459
 460 typedef struct BIUCFG_Cluster {
 461     uint32 permission;        /* 0x0 */
 462     uint32 config;            /* 0x4 */
 463     uint32 status;            /* 0x8 */
 464     uint32 control;           /* 0xc */
 465     uint32 cpucfg;            /* 0x10 */
 466     uint32 dbgrom;            /* 0x14 */
 467     uint32 rsvd1[2];          /* 0x18 - 0x1f */
 468     uint64 rvbar_addr[4];     /* 0x20 - 0x3f */
 469     uint32 rsvd2[48];         /* 0x40 - 0xff */
 470 }BIUCFG_Cluster;
 471
 472 typedef struct BIUCFG_Bac {
 473     uint32 bac_permission;    /* 0x00 */
 474     uint32 bac_periphbase;    /* 0x04 */
 475     uint32 rsvd[2];           /* 0x08 - 0x0f */
 476     uint32 bac_event;         /* 0x10 */
 477     uint32 rsvd_1[3];         /* 0x14 - 0x1f */
 478     uint32 bac_ccicfg;        /* 0x20 */
 479     uint32 bac_cciaddr;       /* 0x24 */
 480     uint32 rsvd_2[4];         /* 0x28 - 0x37 */
 481     uint32 bac_ccievs2;       /* 0x38 */
 482     uint32 bac_ccievs3;       /* 0x3c */
 483     uint32 bac_ccievs4;       /* 0x40 */
 484     uint32 rsvd_3[3];         /* 0x44 - 0x4f */
 485     uint32 bac_ccievm0;       /* 0x50 */
 486     uint32 bac_ccievm1;       /* 0x54 */
 487     uint32 rsvd_4[2];         /* 0x58 - 0x5f */
 488     uint32 bac_dapapbcfg;     /* 0x60 */
 489     uint32 bac_status;        /* 0x64 */
 490     uint32 rsvd_5[2];         /* 0x68 - 0x6f */
 491     uint32 cpu_therm_irq_cfg; /* 0x70 */
 492     uint32 cpu_therm_threshold_cfg; /* 0x74 */
 493     uint32 rsvd_6;            /* 0x78 */
 494     uint32 cpu_therm_temp;    /* 0x7c */
 495     uint32 rsvd_7[32];        /* 0x80 - 0xff */
 496 } BIUCFG_Bac;
 497
 498 typedef struct BIUCFG_Aux {
 499     uint32 aux_permission;    /* 0x00 */
 500     uint32 rsvd[3];           /* 0x04 - 0x0f */
 501     uint32 c0_clk_control;    /* 0x10 */
 502     uint32 c0_clk_ramp;       /* 0x14 */
 503     uint32 c0_clk_pattern;    /* 0x18 */
 504     uint32 rsvd_1;            /* 0x1c */
 505     uint32 c1_clk_control;    /* 0x20 */
 506     uint32 c1_clk_ramp;       /* 0x24 */
 507     uint32 c1_clk_pattern;    /* 0x28 */
 508     uint32 rsvd_2[53];        /* 0x2c - 0xff */
 509 } BIUCFG_Aux;
 510
 511 typedef struct BIUCFG {
 512     BIUCFG_Access access;         /* 0x0 - 0xff*/
 513     BIUCFG_Cluster cluster[2];    /* 0x100 - 0x2ff*/
 514     BIUCFG_Bac bac;               /* 0x300 - 0x3ff */
 515     uint32 anonymous[192];        /* 0x400 - 0x6ff */
 516     BIUCFG_Aux aux;               /* 0x700 - 0x7ff */
 517     uint32 anonymous_1[2560];     /* 0x800 - 0x2fff */
 518 }BIUCFG;
 519
 520 #define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE)
 521
 522
 523 #endif /* __ASSEMBLER__ */
 524
 525 #ifdef __cplusplus
 526 }
 527 #endif
 528
 529 #endif
 530