plat/bcm/include/bcm963xx/4908_map_part.h

   1 /*
   2 <:copyright-BRCM:2013:DUAL/GPL:standard
   3
   4    Copyright (c) 2013 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef __BCM4908_MAP_PART_H
  25 #define __BCM4908_MAP_PART_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #include "bcmtypes.h"
  32
  33 #define MEMC_PHYS_BASE          0x80018000  /* DDR IO Buf Control */
  34 #define MEMC_SIZE               0x4000
  35
  36 #define PMC_PHYS_BASE           0x80200000
  37 #define PMC_SIZE                0x5000
  38 #define PMC_OFFSET              0x0000
  39 #define PROC_MON_PHYS_BASE      0x80280000
  40 #define PROC_MON_SIZE           0x1000
  41 #define PROC_MON_OFFSET         0x0000
  42
  43 /* Perf block base address and size */
  44 #define PERF_PHYS_BASE          0xff800000
  45 #define PERF_SIZE               0x3000
  46 #define TIMR_OFFSET             0x0400   /* timer registers */
  47
  48 #define URB_PHYS_BASE           0x81060000
  49 #define URB_SIZE                0x4000
  50 #define URB_OFFSET              0x0000
  51 #define URB_BIUARCH_OFFSET      0x1000
  52 #define URB_BIUCTRL_OFFSET      0x2000
  53
  54 #define GIC_PHYS_BASE           0x81000000
  55 #define GIC_SIZE                0x10000
  56 #define GIC_OFFSET              0x0000
  57 #define GICD_OFFSET             0x1000
  58 #define GICC_OFFSET             0x2000
  59
  60 #define PMC_BASE                (PMC_PHYS_BASE + PMC_OFFSET)
  61 #define PROC_MON_BASE           (PROC_MON_PHYS_BASE + PROC_MON_OFFSET)
  62
  63 #define URB_BASE                (URB_PHYS_BASE + URB_OFFSET)
  64 #define BIUARCH_BASE            (URB_PHYS_BASE + URB_BIUARCH_OFFSET)
  65 #define BIUCTRL_BASE            (URB_PHYS_BASE + URB_BIUCTRL_OFFSET)
  66
  67 #ifndef __ASSEMBLER__
  68
  69 /*
  70  * Power Management Control
  71  */
  72 typedef struct PmcCtrlReg {
  73    /* 0x00 */
  74    uint32 l1Irq4keMask;
  75    uint32 l1Irq4keStatus;
  76    uint32 l1IrqMipsMask;
  77    uint32 l1IrqMipsStatus;
  78    /* 0x10 */
  79    uint32 l2IrqGpMask;
  80    uint32 l2IrqGpStatus;
  81    uint32 gpTmr0Ctl;
  82    uint32 gpTmr0Cnt;
  83    /* 0x20 */
  84    uint32 gpTmr1Ctl;
  85    uint32 gpTmr1Cnt;
  86    uint32 hostMboxIn;
  87    uint32 hostMboxOut;
  88    /* 0x30 */
  89 #define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
  90    uint32 gpOut;
  91    uint32 gpIn;
  92    uint32 gpInIrqMask;
  93    uint32 gpInIrqStatus;
  94    /* 0x40 */
  95    uint32 dmaCtrl;
  96    uint32 dmaStatus;
  97    uint32 dma0_3FifoStatus;
  98    uint32 unused0[3];   /* 0x4c-0x57 */
  99    /* 0x58 */
 100    uint32 l1IrqMips1Mask;
 101    uint32 diagControl;
 102    /* 0x60 */
 103    uint32 diagHigh;
 104    uint32 diagLow;
 105    uint32 badAddr;
 106    uint32 addr1WndwMask;
 107    /* 0x70 */
 108    uint32 addr1WndwBaseIn;
 109    uint32 addr1WndwBaseOut;
 110    uint32 addr2WndwMask;
 111    uint32 addr2WndwBaseIn;
 112    /* 0x80 */
 113    uint32 addr2WndwBaseOut;
 114    uint32 scratch;
 115    uint32 tm;
 116    uint32 softResets;
 117    /* 0x90 */
 118    uint32 eb2ubusTimeout;
 119    uint32 m4keCoreStatus;
 120    uint32 gpInIrqSense;
 121    uint32 ubSlaveTimeout;
 122    /* 0xa0 */
 123    uint32 diagEn;
 124    uint32 devTimeout;
 125    uint32 ubusErrorOutMask;
 126    uint32 diagCaptStopMask;
 127    /* 0xb0 */
 128    uint32 revId;
 129    uint32 gpTmr2Ctl;
 130    uint32 gpTmr2Cnt;
 131    uint32 legacyMode;
 132    /* 0xc0 */
 133    uint32 smisbMonitor;
 134    uint32 diagCtrl;
 135    uint32 diagStat;
 136    uint32 diagMask;
 137    /* 0xd0 */
 138    uint32 diagRslt;
 139    uint32 diagCmp;
 140    uint32 diagCapt;
 141    uint32 diagCnt;
 142    /* 0xe0 */
 143    uint32 diagEdgeCnt;
 144    uint32 unused1[4];   /* 0xe4-0xf3 */
 145    /* 0xf4 */
 146    uint32 iopPeriphBaseAddr;
 147    uint32 lfsr;
 148    uint32 unused2;      /* 0xfc-0xff */
 149 } PmcCtrlReg;
 150
 151 typedef struct PmcOutFifoReg {
 152    uint32 msgCtrl;      /* 0x00 */
 153    uint32 msgSts;       /* 0x04 */
 154    uint32 unused[14];   /* 0x08-0x3f */
 155    uint32 msgData[16];  /* 0x40-0x7c */
 156 } PmcOutFifoReg;
 157
 158 typedef struct PmcInFifoReg {
 159    uint32 msgCtrl;      /* 0x00 */
 160    uint32 msgSts;       /* 0x04 */
 161    uint32 unused[13];   /* 0x08-0x3b */
 162    uint32 msgLast;      /* 0x3c */
 163    uint32 msgData[16];  /* 0x40-0x7c */
 164 } PmcInFifoReg;
 165
 166 typedef struct PmcDmaReg {
 167    /* 0x00 */
 168    uint32 src;
 169    uint32 dest;
 170    uint32 cmdList;
 171    uint32 lenCtl;
 172    /* 0x10 */
 173    uint32 rsltSrc;
 174    uint32 rsltDest;
 175    uint32 rsltHcs;
 176    uint32 rsltLenStat;
 177 } PmcDmaReg;
 178
 179 typedef struct PmcTokenReg {
 180    /* 0x00 */
 181    uint32 bufSize;
 182    uint32 bufBase;
 183    uint32 idx2ptrIdx;
 184    uint32 idx2ptrPtr;
 185    /* 0x10 */
 186    uint32 unused[2];
 187    uint32 bufSize2;
 188 } PmcTokenReg;
 189
 190 typedef struct PmcPerfPowReg {
 191    /* 0x00 */
 192    uint32 dcacheHit;
 193    uint32 dcacheMiss;
 194    uint32 icacheHit;
 195    uint32 icacheMiss;
 196    /* 0x10 */
 197    uint32 instnComplete;
 198    uint32 wtbMerge;
 199    uint32 wtbNoMerge;
 200    uint32 itlbHit;
 201    /* 0x20 */
 202    uint32 itlbMiss;
 203    uint32 dtlbHit;
 204    uint32 dtlbMiss;
 205    uint32 jtlbHit;
 206    /* 0x30 */
 207    uint32 jtlbMiss;
 208    uint32 powerSubZone;
 209    uint32 powerMemPda;
 210    uint32 freqScalarCtrl;
 211    /* 0x40 */
 212    uint32 freqScalarMask;
 213 } PmcPerfPowReg;
 214
 215 typedef struct PmcDQMReg {
 216    /* 0x00 */
 217    uint32 cfg;
 218    uint32 _4keLowWtmkIrqMask;
 219    uint32 mipsLowWtmkIrqMask;
 220    uint32 lowWtmkIrqMask;
 221    /* 0x10 */
 222    uint32 _4keNotEmptyIrqMask;
 223    uint32 mipsNotEmptyIrqMask;
 224    uint32 notEmptyIrqSts;
 225    uint32 queueRst;
 226    /* 0x20 */
 227    uint32 notEmptySts;
 228    uint32 nextAvailMask;
 229    uint32 nextAvailQueue;
 230    uint32 mips1LowWtmkIrqMask;
 231    /* 0x30 */
 232    uint32 mips1NotEmptyIrqMask;
 233    uint32 autoSrcPidInsert;
 234 } PmcDQMReg;
 235
 236 typedef struct PmcCntReg {
 237    uint32 cntr[10];
 238    uint32 unused[6]; /* 0x28-0x3f */
 239    uint32 cntrIrqMask;
 240    uint32 cntrIrqSts;
 241 } PmcCntReg;
 242
 243 typedef struct PmcDqmQCtrlReg {
 244    uint32 size;
 245    uint32 cfga;
 246    uint32 cfgb;
 247    uint32 cfgc;
 248 } PmcDqmQCtrlReg;
 249
 250 typedef struct PmcDqmQDataReg {
 251    uint32 word[4];
 252 } PmcDqmQDataReg;
 253
 254 typedef struct PmcDqmQMibReg {
 255    uint32 qNumFull[32];
 256    uint32 qNumEmpty[32];
 257    uint32 qNumPushed[32];
 258 } PmcDqmQMibReg;
 259
 260 typedef struct Pmc {
 261    uint32 baseReserved;    /* 0x0000 */
 262    uint32 unused0[1023];
 263    PmcCtrlReg ctrl;     /* 0x1000 */
 264
 265    PmcOutFifoReg outFifo;     /* 0x1100 */
 266    uint32 unused1[32];     /* 0x1180-0x11ff */
 267    PmcInFifoReg inFifo;    /* 0x1200 */
 268    uint32 unused2[32];     /* 0x1280-0x12ff */
 269
 270    PmcDmaReg dma[2];    /* 0x1300 */
 271    uint32 unused3[48];     /* 0x1340-0x13ff */
 272
 273    PmcTokenReg token;      /* 0x1400 */
 274    uint32 unused4[121];    /* 0x141c-0x15ff */
 275
 276    PmcPerfPowReg perfPower;   /* 0x1600 */
 277    uint32 unused5[47];     /* 0x1644-0x16ff */
 278
 279    uint32 msgId[32];    /* 0x1700 */
 280    uint32 unused6[32];     /* 0x1780-0x17ff */
 281
 282    PmcDQMReg dqm;       /* 0x1800 */
 283    uint32 unused7[50];     /* 0x1838-0x18ff */
 284
 285    PmcCntReg hwCounter;    /* 0x1900 */
 286    uint32 unused8[46];     /* 0x1948-0x19ff */
 287
 288    PmcDqmQCtrlReg dqmQCtrl[32];  /* 0x1a00 */
 289    PmcDqmQDataReg dqmQData[32];  /* 0x1c00 */
 290    uint32 unused9[64];     /* 0x1e00-0x1eff */
 291
 292    uint32 qStatus[32];     /* 0x1f00 */
 293    uint32 unused10[32];    /* 0x1f80-0x1fff */
 294
 295    PmcDqmQMibReg qMib;     /* 0x2000 */
 296    uint32 unused11[1952];     /* 0x2180-0x3ffff */
 297
 298    uint32 sharedMem[512];    /* 0x4000-0x47ff */
 299 } Pmc;
 300
 301 #define PMC ((volatile Pmc * const) PMC_BASE)
 302
 303 /*
 304  * Process Monitor Module
 305  */
 306 typedef struct PMRingOscillatorControl {
 307    uint32 control;
 308    uint32 en_lo;
 309    uint32 en_mid;
 310    uint32 en_hi;
 311    uint32 idle_lo;
 312    uint32 idle_mid;
 313    uint32 idle_hi;
 314 } PMRingOscillatorControl;
 315
 316 #define RCAL_0P25UM_HORZ          0
 317 #define RCAL_0P25UM_VERT          1
 318 #define RCAL_0P5UM_HORZ           2
 319 #define RCAL_0P5UM_VERT           3
 320 #define RCAL_1UM_HORZ             4
 321 #define RCAL_1UM_VERT             5
 322 #define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
 323 #define PMMISC_RMON_VALID_MASK    (0x1<<16)
 324 typedef struct PMMiscControl {
 325    uint32 gp_out;
 326    uint32 clock_select;
 327    uint32 unused[2];
 328    uint32 misc[4];
 329 } PMMiscControl;
 330
 331 typedef struct PMSSBMasterControl {
 332    uint32 control;
 333 #define PMC_SSBM_CONTROL_SSB_START  (1<<15)
 334 #define PMC_SSBM_CONTROL_SSB_ADPRE  (1<<13)
 335 #define PMC_SSBM_CONTROL_SSB_EN     (1<<12)
 336 #define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10)
 337 #define PMC_SSBM_CONTROL_SSB_CMD_MASK  (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
 338 #define PMC_SSBM_CONTROL_SSB_CMD_READ  (2)
 339 #define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1)
 340 #define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT   (0)
 341 #define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
 342    uint32 wr_data;
 343    uint32 rd_data;
 344 } PMSSBMasterControl;
 345
 346 typedef struct PMEctrControl {
 347    uint32 control;
 348    uint32 interval;
 349    uint32 thresh_lo;
 350    uint32 thresh_hi;
 351    uint32 count;
 352 } PMEctrControl;
 353
 354 typedef struct PMBMaster {
 355    uint32 ctrl;
 356 #define PMC_PMBM_START     (1 << 31)
 357 #define PMC_PMBM_TIMEOUT   (1 << 30)
 358 #define PMC_PMBM_SLAVE_ERR (1 << 29)
 359 #define PMC_PMBM_BUSY      (1 << 28)
 360 #define PMC_PMBM_Read      (0 << 20)
 361 #define PMC_PMBM_Write     (1 << 20)
 362    uint32 wr_data;
 363    uint32 timeout;
 364    uint32 rd_data;
 365    uint32 unused[4];
 366 } PMBMaster;
 367
 368 typedef struct PMAPVTMONControl {
 369    uint32 control;
 370    uint32 reserved;
 371    uint32 cfg_lo;
 372    uint32 cfg_hi;
 373    uint32 data;
 374    uint32 vref_data;
 375    uint32 unused[2];
 376    uint32 ascan_cfg;
 377    uint32 warn_temp;
 378    uint32 reset_temp;
 379    uint32 temp_value;
 380    uint32 data1_value;
 381    uint32 data2_value;
 382    uint32 data3_value;
 383 } PMAPVTMONControl;
 384
 385 typedef struct PMUBUSCfg {
 386    uint32 window[8];
 387    uint32 control;
 388 } PMUBUSCfg;
 389
 390 typedef struct ProcessMonitorRegs {
 391    uint32 MonitorCtrl;     /* 0x00 */
 392    uint32 unused0[7];
 393    PMRingOscillatorControl ROSC; /* 0x20 */
 394    uint32 unused1;
 395    PMMiscControl Misc;     /* 0x40 */
 396    PMSSBMasterControl SSBMaster; /* 0x60 */
 397    uint32 unused2[5];
 398    PMEctrControl Ectr;     /* 0x80 */
 399    uint32 unused3[11];
 400    PMBMaster PMBM[2];      /* 0xc0 */
 401    PMAPVTMONControl APvtmonCtrl; /* 0x100 */
 402    uint32 unused4[9];
 403    PMUBUSCfg UBUSCfg;      /* 0x160 */
 404 } ProcessMonitorRegs;
 405
 406 #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
 407
 408 /*
 409  * URB UBUS RBUS Block register
 410  */
 411 typedef struct BIUArchRegion {
 412     uint32 addr_ulimit;
 413     uint32 addr_llimit;
 414     uint32 permission;
 415     uint32 access_right_ctrl;
 416 } BIUArchRegion;
 417
 418 typedef struct BIUArch {
 419     BIUArchRegion region[8];    /* 0x0 */
 420     uint32 unused[95];          /* 0x80 */
 421     uint32 scratch;             /* 0x1fc */
 422 } BIUArch;
 423
 424 #define BIUARCH ((volatile BIUArch * const) BIUARCH_BASE)
 425
 426 typedef struct BIUCpuBusRange {
 427 #define ULIMIT_SHIFT 4
 428 #define BUSNUM_MASK 0x0000000FU
 429
 430 #define BUSNUM_UBUS 1
 431 #define BUSNUM_RBUS 2
 432 #define BUSNUM_RSVD 3
 433 #define BUSNUM_MCP0 4
 434 #define BUSNUM_MCP1 5
 435 #define BUSNUM_MCP2 6
 436
 437     uint32 ulimit;
 438     uint32 llimit;
 439 } BIUCpuBusRange;
 440
 441 typedef struct BIUCpuAccessRightViol {
 442     uint32 addr;
 443     uint32 upper_addr;
 444     uint32 detail_addr;
 445 } BIUCpuAccessRightViol;
 446
 447 typedef struct BIUCpuBPCMAVS {
 448     uint32 bpcm_id;
 449     uint32 bpcm_capability;
 450 } BIUCpuBPCMAVS;
 451
 452 typedef struct BIUCtrl {
 453     BIUCpuBusRange bus_range[11];                   /* 0x0 */
 454     uint32 secure_reset_hndshake;
 455     uint32 secure_soft_reset;
 456     BIUCpuAccessRightViol access_right_viol[2];     /* 0x60 */
 457     uint32 rac_cfg0;
 458     uint32 rac_cfg1;
 459     uint32 rac_cfg2;                                /* 0x80 */
 460     uint32 rac_flush;
 461     uint32 power_cfg;
 462 #define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT 4
 463 #define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON      (0x1<<BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT)
 464     uint32 reset_cfg;
 465 #define BIU_CPU_CTRL_RST_CFG_CPU0_RESET_SHIFT       0
 466 #define BIU_CPU_CTRL_RST_CFG_CPU0_RESET             (0x1<<BIU_CPU_CTRL_RST_CFG_CPU0_RESET_SHIFT)
 467     uint32 clock_cfg;                               /* 0x90 */
 468 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT    8
 469 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_MASK     (0xf<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
 470 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV1     (0<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
 471 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV2     (1<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
 472 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV3     (2<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
 473 #define BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_DIV4     (3<<BIU_CPU_CTRL_CLK_CFG_CCI_CLK_RATIO_SHIFT)
 474 #define BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_SHIFT  4
 475 #define BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_MASK   (1<<BIU_CPU_CTRL_CLK_CFG_SAFE_CLOCK_MODE_SHIFT)
 476 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT        0
 477 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_MASK         (0xf<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 478 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV1         (0<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 479 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV2         (1<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 480 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV4         (2<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 481 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV8         (3<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 482 #define BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_DIV16        (4<<BIU_CPU_CTRL_CLK_CFG_CLK_RATIO_SHIFT)
 483     uint32 cluster_clk_ctrl[2];
 484     uint32 cluster_clk_pattern[2];
 485     uint32 cluster_clk_ramp[2];
 486     uint32 misc_cfg;
 487     uint32 credit;                                  /* 0xb0 */
 488     uint32 mcp_flow;
 489     uint32 periphbase_gic;
 490     uint32 periphbase_gic_web;
 491     uint32 wfx_state;                               /* 0xc0 */
 492     uint32 cpu_pwr_zone_ctrl[8];
 493 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET_SHIFT 31
 494 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET_SHIFT)
 495 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ_SHIFT 10
 496 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ_SHIFT)
 497 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ_SHIFT 9
 498 #define BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ       (1<<BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ_SHIFT)
 499     uint32 cpu_pwr_zone_cfg1[8];
 500     uint32 cpu_pwr_zone_cfg2[8];
 501     uint32 c0l2_pwr_zone_ctrl;                      /* 0x124 */
 502     uint32 c0l2_pwr_zone_cfg1;
 503     uint32 c0l2_pwr_zone_cfg2;
 504     uint32 c1l2_pwr_zone_ctrl;
 505     uint32 c1l2_pwr_zone_cfg1;
 506     uint32 c1l2_pwr_zone_cfg2;
 507     uint32 sysif_pwr_zone_ctrl;
 508     uint32 sysif_pwr_zone_cfg1;
 509     uint32 sysif_pwr_zone_cfg2;
 510     BIUCpuBPCMAVS cpu_bpcm_avs[8];                  /* 0x148 */
 511     BIUCpuBPCMAVS l2biu_bpcm_avs[3];                /* 0x188 */
 512     uint32 therm_throttle_temp;                     /* 0x1a0 */
 513     uint32 term_throttle_irq_cfg;
 514     uint32 therm_irq_high;
 515     uint32 therm_irq_low;
 516     uint32 therm_misc_threshold;                    /* 0x1b0 */
 517     uint32 therm_irq_misc;
 518     uint32 defeature;
 519     uint32 defeature2;
 520     uint32 defeature_key;                           /* 0x1c0 */
 521     uint32 debug_rom_addr;
 522     uint32 debug_tracectrl;
 523     uint32 axi_cfg;
 524     uint32 revision;                                /* 0x1d0 */
 525     uint32 patchlevel;
 526     uint32 ubus_cfg;                                /* 0x1d8 */
 527     uint32 ubus_cfg_window[8];
 528     uint32 power_state;
 529     uint32 phys_config;                             /* 0x200 */
 530     uint32 unused[126];                             /* 0x204 */
 531     uint32 scratch;                                 /* 0x3fc */
 532 } BIUCtrl;
 533
 534 #define BIUCTRL ((volatile BIUCtrl * const) BIUCTRL_BASE)
 535
 536 typedef struct URB_Ctrl {
 537     uint32 unused0[1024];                           /* 0x0000 */
 538     BIUArch arch;                                   /* 0x1000 */
 539     uint32 unused1[896];                            /* 0x1200 */
 540     BIUCtrl cpu_ctrl;                               /* 0x2000 */
 541 } URB_Ctrl;
 542
 543 #define URB_CTRL ((volatile URB_Ctrl *const) URB_BASE)
 544
 545 #endif /* __ASSEMBLER__ */
 546
 547 #ifdef __cplusplus
 548 }
 549 #endif
 550
 551 #endif
 552