plat/bcm/brcm_bl31_setup.c

   1 /*
   2  * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <arch_helpers.h>
   9 #include <assert.h>
  10 #include <bl_common.h>
  11 #include <console.h>
  12 #include <debug.h>
  13 #include <mmio.h>
  14 #include <plat_arm.h>
  15 #include <platform.h>
  16 #include <gicv2.h>
  17 #include <string.h>
  18 #include <generic_delay_timer.h>
  19 #include <delay_timer.h>
  20
  21 #define BL31_END (uintptr_t)(&__BL31_END__)
  22
  23 #define MAP_BL31_TOTAL  MAP_REGION_FLAT(                        \
  24                                         BL31_BASE,                      \
  25                                         BL31_END - BL31_BASE,           \
  26                                         MT_MEMORY | MT_RW | MT_SECURE)
  27
  28 #define ARM_MAP_BL_RO                   MAP_REGION_FLAT(                        \
  29                                                 BL_CODE_BASE,                   \
  30                                                 BL_CODE_END - BL_CODE_BASE,     \
  31                                                 MT_CODE | MT_SECURE)
  32
  33 #define ARM_MAP_BL_COHERENT_RAM         MAP_REGION_FLAT(                        \
  34                                                 BL_COHERENT_RAM_BASE,           \
  35                                                 BL_COHERENT_RAM_END             \
  36                                                         - BL_COHERENT_RAM_BASE, \
  37                                                 MT_DEVICE | MT_RW | MT_SECURE)
  38
  39 /*
  40  * Placeholder variables for copying the arguments that have been passed to
  41  * BL31 from BL2.
  42  */
  43 static entry_point_info_t bl32_image_ep_info;
  44 static entry_point_info_t bl33_image_ep_info;
  45
  46 static uintptr_t ns_entry_point;
  47
  48 #define DEVICE_BASE  0x80000000
  49 #define DEVICE_SIZE  0x00010000
  50
  51 const mmap_region_t plat_arm_mmap[] = {
  52   MAP_REGION_FLAT(DEVICE_BASE,  DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
  53   MAP_REGION_FLAT(GICD_BASE,    DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
  54   MAP_REGION_FLAT(UART0_BASE,   UART0_SIZE,  MT_DEVICE | MT_RW | MT_SECURE),
  55 #if defined(BIUCFG_BASE)
  56   MAP_REGION_FLAT(BIUCFG_BASE,  BIUCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
  57 #elif defined(BIUCTRL_BASE)
  58   MAP_REGION_FLAT(BIUCTRL_BASE, BIUCTRL_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
  59 #endif
  60   MAP_REGION_FLAT(BOOTLUT_BASE, BOOTLUT_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
  61 #if defined(WDTIMR0_BASE)
  62   MAP_REGION_FLAT(WDTIMR_BASE,  WDTIMR_SIZE,  MT_DEVICE | MT_RW | MT_SECURE),
  63 #endif
  64   MAP_REGION_FLAT(PMC_BASE,     PMC_SIZE,    MT_DEVICE | MT_RW | MT_SECURE),
  65   {0}
  66 };
  67
  68
  69 /*******************************************************************************
  70  * Return a pointer to the 'entry_point_info' structure of the next image for the
  71  * security state specified. BL33 corresponds to the non-secure image type
  72  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  73  * if the image does not exist.
  74  ******************************************************************************/
  75 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  76 {
  77         entry_point_info_t *next_image_info;
  78
  79         assert(sec_state_is_valid(type));
  80         next_image_info = (type == NON_SECURE)
  81                         ? &bl33_image_ep_info : &bl32_image_ep_info;
  82         /*
  83          * None of the images on the ARM development platforms can have 0x0
  84          * as the entrypoint
  85          */
  86         if (next_image_info->pc)
  87                 return next_image_info;
  88         else
  89                 return NULL;
  90 }
  91
  92 /*******************************************************************************
  93  * Obtain ns entry point
  94  ******************************************************************************/
  95 uintptr_t plat_get_ns_image_entrypoint(void)
  96 {
  97         return ns_entry_point;
  98 }
  99
 100 /*******************************************************************************
 101  * Set ns-entry point
 102  ******************************************************************************/
 103 void plat_set_ns_image_entrypoint(uintptr_t entry_point)
 104 {
 105         ns_entry_point = entry_point;
 106 }
 107
 108
 109 struct atf_image_info {
 110         struct param_header h;
 111         uintptr_t image_base;   /* physical address of base of image */
 112         uint32_t image_size;    /* bytes read from image file */
 113 };
 114
 115 struct atf_entry_point_info {
 116         struct param_header h;
 117         uintptr_t pc;
 118         uint32_t spsr;
 119         struct aapcs64_params args;
 120 };
 121
 122 typedef struct bl31_params {
 123         param_header_t h;
 124         struct atf_image_info *bl31_image_info;
 125         struct atf_entry_point_info *bl32_ep_info;
 126         struct atf_image_info *bl32_image_info;
 127         struct atf_entry_point_info *bl33_ep_info;
 128         struct atf_image_info *bl33_image_info;
 129 } bl31_params_t;
 130
 131 /*******************************************************************************
 132  * Perform any BL31 early platform setup common to ARM standard platforms.
 133  * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
 134  * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
 135  * done before the MMU is initialized so that the memory layout can be used
 136  * while creating page tables. BL2 has flushed this information to memory, so
 137  * we are guaranteed to pick up good data.
 138  ******************************************************************************/
 139 void arm_bl31_early_platform_setup(void *param0, uintptr_t plat_params_from_bl2, uintptr_t arg2, void * arg43)
 140 {
 141         bl31_params_t *from_bl2 = (bl31_params_t *)param0;
 142
 143 #ifdef BL32_BASE
 144         /* Populate entry point information for BL32 */
 145         SET_PARAM_HEAD(&bl32_image_ep_info,
 146                                 PARAM_EP,
 147                                 VERSION_1,
 148                                 0);
 149         SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
 150         bl32_image_ep_info.pc = BL32_BASE;
 151         bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
 152         /* Provide boot parameters to OPTEE */
 153         memset(&bl32_image_ep_info.args, 0, sizeof(aapcs64_params_t));
 154         bl32_image_ep_info.args.arg0 = MODE_RW_64;
 155         bl32_image_ep_info.args.arg2 = (u_register_t)plat_params_from_bl2;
 156 #endif /* BL32_BASE */
 157
 158         /* Populate entry point information for BL33 */
 159         SET_PARAM_HEAD(&bl33_image_ep_info,
 160                                 PARAM_EP,
 161                                 VERSION_1,
 162                                 0);
 163
 164         /* Configure ns entry point */
 165         plat_set_ns_image_entrypoint(from_bl2->bl33_ep_info->pc);
 166
 167         /*
 168          * Tell BL31 where the non-trusted software image
 169          * is located and the entry state information
 170          */
 171         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 172
 173         bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
 174         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 175
 176         /*
 177         * Provide Linux DTB address
 178         */
 179         bl33_image_ep_info.args.arg0 = (u_register_t)from_bl2;
 180         bl33_image_ep_info.args.arg1 = (u_register_t)plat_get_ns_image_entrypoint();
 181 }
 182
 183 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2,
 184                                 u_register_t arg3)
 185 {
 186         arm_bl31_early_platform_setup((void*)arg0, (uintptr_t)arg1, arg2, (void*)arg3);
 187 }
 188
 189 #define PLATFORM_G1S_PROPS(grp)                                         \
 190         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,    \
 191                                            grp, GIC_INTR_CFG_LEVEL),    \
 192         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,    \
 193                                            grp, GIC_INTR_CFG_LEVEL),    \
 194         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,    \
 195                                            grp, GIC_INTR_CFG_LEVEL),    \
 196         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,    \
 197                                            grp, GIC_INTR_CFG_LEVEL),    \
 198         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,    \
 199                                            grp, GIC_INTR_CFG_LEVEL),    \
 200         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,    \
 201                                            grp, GIC_INTR_CFG_LEVEL),    \
 202         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,    \
 203                                            grp, GIC_INTR_CFG_LEVEL),    \
 204         INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,    \
 205                                            grp, GIC_INTR_CFG_LEVEL)
 206
 207
 208 static const interrupt_prop_t irq_sec_array[] = {
 209         PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0)
 210 };
 211
 212 static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
 213
 214 static const struct gicv2_driver_data plat_gicv2_driver_data = {
 215         .gicd_base = GICD_BASE,
 216         .gicc_base = GICC_BASE,
 217         .interrupt_props = irq_sec_array,
 218         .interrupt_props_num = ARRAY_SIZE(irq_sec_array),
 219         .target_masks = target_mask_array,
 220         .target_masks_num = ARRAY_SIZE(target_mask_array),
 221 };
 222
 223 /*******************************************************************************
 224  * Perform any BL31 platform setup common to ARM standard platforms
 225  ******************************************************************************/
 226 void arm_bl31_platform_setup(void)
 227 {
 228         /* Initialize the gic cpu and distributor interfaces */
 229         gicv2_driver_init(&plat_gicv2_driver_data);
 230         gicv2_distif_init();
 231         gicv2_pcpu_distif_init();
 232         gicv2_cpuif_enable();
 233 }
 234
 235 /*******************************************************************************
 236  * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
 237  * standard platforms
 238  ******************************************************************************/
 239 void arm_bl31_plat_runtime_setup(void)
 240 {
 241         /* Initialize the runtime functions */
 242 }
 243
 244 void bl31_platform_setup(void)
 245 {
 246         arm_bl31_platform_setup();
 247 }
 248
 249 void bl31_plat_runtime_setup(void)
 250 {
 251         arm_bl31_plat_runtime_setup();
 252 }
 253
 254 /*******************************************************************************
 255  * Perform the very early platform specific architectural setup shared between
 256  * ARM standard platforms. This only does basic initialization. Later
 257  * architectural setup (bl31_arch_setup()) does not do anything platform
 258  * specific.
 259  ******************************************************************************/
 260 void arm_bl31_plat_arch_setup(void)
 261 {
 262         const mmap_region_t bl_regions[] = {
 263                 MAP_BL31_TOTAL,
 264                 ARM_MAP_BL_RO,
 265 #if USE_COHERENT_MEM
 266                 ARM_MAP_BL_COHERENT_RAM,
 267 #endif
 268                 {0}
 269         };
 270
 271         setup_page_tables(bl_regions, plat_arm_get_mmap());
 272
 273         generic_delay_timer_init();
 274
 275         enable_mmu_el3(0);
 276 }
 277
 278 void bl31_plat_arch_setup(void)
 279 {
 280         arm_bl31_plat_arch_setup();
 281 }
 282
 283 unsigned int plat_get_syscnt_freq2(void)
 284 {
 285         return SYS_COUNTER_FREQ_IN_TICKS;
 286 }