docs/plat/intel-stratix10.rst

   1 Intel Stratix 10 SoCFPGA
   2 ========================
   3
   4 Stratix 10 SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.
   5
   6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
   7 the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
   8
   9 ::
  10
  11     Boot ROM --> Trusted Firmware-A --> UEFI
  12
  13 How to build
  14 ------------
  15
  16 Code Locations
  17 ~~~~~~~~~~~~~~
  18
  19 -  Trusted Firmware-A:
  20    `link <https://github.com/ARM-software/arm-trusted-firmware>`__
  21
  22 -  UEFI (to be updated with new upstreamed UEFI):
  23    `link <https://github.com/altera-opensource/uefi-socfpga>`__
  24
  25 Build Procedure
  26 ~~~~~~~~~~~~~~~
  27
  28 -  Fetch all the above 2 repositories into local host.
  29    Make all the repositories in the same ${BUILD\_PATH}.
  30
  31 -  Prepare the AARCH64 toolchain.
  32
  33 -  Build UEFI using Stratix 10 platform as configuration
  34    This will be updated to use an updated UEFI using the latest EDK2 source
  35
  36 .. code:: bash
  37
  38        make CROSS_COMPILE=aarch64-linux-gnu- device=s10
  39
  40 -  Build atf providing the previously generated UEFI as the BL33 image
  41
  42 .. code:: bash
  43
  44        make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=stratix10
  45        BL33=PEI.ROM
  46
  47 Install Procedure
  48 ~~~~~~~~~~~~~~~~~
  49
  50 - dd fip.bin to a A2 partition on the MMC drive to be booted in Stratix 10
  51   board.
  52
  53 - Generate a SOF containing bl2
  54
  55 .. code:: bash
  56
  57         aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
  58         quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>
  59
  60 - Configure SOF to board
  61
  62 .. code:: bash
  63
  64         nios2-configure-sof <output_sof_with_bl2>
  65
  66 Boot trace
  67 ----------
  68
  69 ::
  70
  71          INFO:    DDR: DRAM calibration success.
  72          INFO:    ECC is disabled.
  73          INFO:    Init HPS NOC's DDR Scheduler.
  74          NOTICE:  BL2: v2.0(debug):v2.0-809-g7f8474a-dirty
  75          NOTICE:  BL2: Built : 17:38:19, Feb 18 2019
  76          INFO:    BL2: Doing platform setup
  77          INFO:    BL2: Loading image id 3
  78          INFO:    Loading image id=3 at address 0xffe1c000
  79          INFO:    Image id=3 loaded: 0xffe1c000 - 0xffe24034
  80          INFO:    BL2: Loading image id 5
  81          INFO:    Loading image id=5 at address 0x50000
  82          INFO:    Image id=5 loaded: 0x50000 - 0x550000
  83          NOTICE:  BL2: Booting BL31
  84          INFO:    Entry point address = 0xffe1c000
  85          INFO:    SPSR = 0x3cd
  86          NOTICE:  BL31: v2.0(debug):v2.0-810-g788c436-dirty
  87          NOTICE:  BL31: Built : 15:17:16, Feb 20 2019
  88          INFO:    ARM GICv2 driver initialized
  89          INFO:    BL31: Initializing runtime services
  90          WARNING: BL31: cortex_a53: CPU workaround for 855873 was missing!
  91          INFO:    BL31: Preparing for EL3 exit to normal world
  92          INFO:    Entry point address = 0x50000
  93          INFO:    SPSR = 0x3c9
  94          UEFI firmware (version 1.0 built at 11:26:18 on Nov  7 2018)