docs/index.rst

   1 Trusted Firmware-A Documentation
   2 ================================
   3
   4 .. toctree::
   5    :maxdepth: 1
   6    :hidden:
   7
   8    Home<self>
   9    getting_started/index
  10    process/index
  11    components/index
  12    design/index
  13    plat/index
  14    perf/index
  15    security_advisories/index
  16    change-log
  17    acknowledgements
  18    glossary
  19    maintainers
  20    license
  21
  22 .. contents:: On This Page
  23     :depth: 3
  24
  25 Trusted Firmware-A (TF-A) provides a reference implementation of secure world
  26 software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
  27 at Exception Level 3 (EL3). It implements various Arm interface standards,
  28 such as:
  29
  30 -  The `Power State Coordination Interface (PSCI)`_
  31 -  `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
  32 -  `SMC Calling Convention`_
  33 -  `System Control and Management Interface (SCMI)`_
  34 -  `Software Delegated Exception Interface (SDEI)`_
  35
  36 Where possible, the code is designed for reuse or porting to other Armv7-A and
  37 Armv8-A model and hardware platforms.
  38
  39 This release provides a suitable starting point for productization of secure
  40 world boot and runtime firmware, in either the AArch32 or AArch64 execution
  41 states.
  42
  43 Users are encouraged to do their own security validation, including penetration
  44 testing, on any secure world code derived from TF-A.
  45
  46 In collaboration with interested parties, we will continue to enhance |TF-A|
  47 with reference implementations of Arm standards to benefit developers working
  48 with Armv7-A and Armv8-A TrustZone technology.
  49
  50 Functionality
  51 -------------
  52
  53 -  Initialization of the secure world, for example exception vectors, control
  54    registers and interrupts for the platform.
  55
  56 -  Library support for CPU specific reset and power down sequences. This
  57    includes support for errata workarounds and the latest Arm DynamIQ CPUs.
  58
  59 -  Drivers to enable standard initialization of Arm System IP, for example
  60    Generic Interrupt Controller (GIC), Cache Coherent Interconnect (CCI),
  61    Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
  62    Controller (TZC).
  63
  64 -  A generic `SCMI`_ driver to interface with conforming power controllers, for
  65    example the Arm System Control Processor (SCP).
  66
  67 -  SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
  68    Convention`_ using an EL3 runtime services framework.
  69
  70 -  `PSCI`_ library support for CPU, cluster and system power management
  71    use-cases.
  72    This library is pre-integrated with the AArch64 EL3 Runtime Software, and
  73    is also suitable for integration with other AArch32 EL3 Runtime Software,
  74    for example an AArch32 Secure OS.
  75
  76 -  A minimal AArch32 Secure Payload (SP\_MIN) to demonstrate `PSCI`_ library
  77    integration with AArch32 EL3 Runtime Software.
  78
  79 -  Secure Monitor library code such as world switching, EL1 context management
  80    and interrupt routing.
  81    When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
  82    AArch64 EL3 Runtime Software must be integrated with a Secure Payload
  83    Dispatcher (SPD) component to customize the interaction with the SP.
  84
  85 -  A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
  86    interaction with PSCI.
  87
  88 -  SPDs for the `OP-TEE Secure OS`_, `NVIDIA Trusted Little Kernel`_
  89    and `Trusty Secure OS`_.
  90
  91 -  A Trusted Board Boot implementation, conforming to all mandatory TBBR
  92    requirements. This includes image authentication, Firmware Update (or
  93    recovery mode), and packaging of the various firmware images into a
  94    Firmware Image Package (FIP).
  95
  96 -  Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
  97    its hardware Root of Trust and crypto acceleration services.
  98
  99 -  Reliability, Availability, and Serviceability (RAS) functionality, including
 100
 101    -  A Secure Partition Manager (SPM) to manage Secure Partitions in
 102       Secure-EL0, which can be used to implement simple management and
 103       security services.
 104
 105    -  An |SDEI| dispatcher to route interrupt-based |SDEI| events.
 106
 107    -  An Exception Handling Framework (EHF) that allows dispatching of EL3
 108       interrupts to their registered handlers, to facilitate firmware-first
 109       error handling.
 110
 111 -  A dynamic configuration framework that enables each of the firmware images
 112    to be configured at runtime if required by the platform. It also enables
 113    loading of a hardware configuration (for example, a kernel device tree)
 114    as part of the FIP, to be passed through the firmware stages.
 115
 116 -  Support for alternative boot flows, for example to support platforms where
 117    the EL3 Runtime Software is loaded using other firmware or a separate
 118    secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
 119    at EL3.
 120
 121 -  Support for the GCC, LLVM and Arm Compiler 6 toolchains.
 122
 123 -  Support for combining several libraries into a "romlib" image that may be
 124    shared across images to reduce memory footprint. The romlib image is stored
 125    in ROM but is accessed through a jump-table that may be stored
 126    in read-write memory, allowing for the library code to be patched.
 127
 128 -  A prototype implementation of a Secure Partition Manager (SPM) that is based
 129    on the SPCI Alpha 1 and SPRT draft specifications.
 130
 131 -  Support for ARMv8.3 pointer authentication in the normal and secure worlds.
 132    The use of pointer authentication in the normal world is enabled whenever
 133    architectural support is available, without the need for additional build
 134    flags. Use of pointer authentication in the secure world remains an
 135    experimental configuration at this time and requires the
 136    ``BRANCH_PROTECTION`` option to be set to non-zero.
 137
 138 -  Position-Independent Executable (PIE) support. Initially for BL31 only, with
 139    further support to be added in a future release.
 140
 141 For a full description of functionality and implementation details, please
 142 see :ref:`Firmware Design` and supporting documentation. The
 143 :ref:`Change Log & Release Notes` provides details of changes made since the
 144 last release.
 145
 146 Platforms
 147 ---------
 148
 149 Various AArch32 and AArch64 builds of this release have been tested on r0, r1
 150 and r2 variants of the `Juno Arm Development Platform`_.
 151
 152 The latest version of the AArch64 build of TF-A has been tested on the following
 153 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
 154 (64-bit host machine only).
 155
 156 .. note::
 157    The FVP models used are Version 11.6 Build 45, unless otherwise stated.
 158
 159 -  ``FVP_Base_AEMv8A-AEMv8A``
 160 -  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
 161 -  ``FVP_Base_RevC-2xAEMv8A``
 162 -  ``FVP_Base_Cortex-A32x4``
 163 -  ``FVP_Base_Cortex-A35x4``
 164 -  ``FVP_Base_Cortex-A53x4``
 165 -  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
 166 -  ``FVP_Base_Cortex-A55x4``
 167 -  ``FVP_Base_Cortex-A57x1-A53x1``
 168 -  ``FVP_Base_Cortex-A57x2-A53x4``
 169 -  ``FVP_Base_Cortex-A57x4-A53x4``
 170 -  ``FVP_Base_Cortex-A57x4``
 171 -  ``FVP_Base_Cortex-A72x4-A53x4``
 172 -  ``FVP_Base_Cortex-A72x4``
 173 -  ``FVP_Base_Cortex-A73x4-A53x4``
 174 -  ``FVP_Base_Cortex-A73x4``
 175 -  ``FVP_Base_Cortex-A75x4``
 176 -  ``FVP_Base_Cortex-A76x4``
 177 -  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
 178 -  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
 179 -  ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
 180 -  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
 181 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
 182 -  ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
 183 -  ``FVP_RD_E1Edge`` (Version 11.3 build 42)
 184 -  ``FVP_RD_N1Edge`` (Version 11.3 build 42)
 185 -  ``Foundation_Platform``
 186
 187 The latest version of the AArch32 build of TF-A has been tested on the following
 188 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
 189 (64-bit host machine only).
 190
 191 -  ``FVP_Base_AEMv8A-AEMv8A``
 192 -  ``FVP_Base_Cortex-A32x4``
 193
 194 .. note::
 195    The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities.
 196
 197 The Foundation FVP can be downloaded free of charge. The Base FVPs can be
 198 licensed from Arm. See the `Arm FVP website`_.
 199
 200 All the above platforms have been tested with `Linaro Release 19.06`_.
 201
 202 This release also contains the following platform support:
 203
 204 -  Allwinner sun50i_a64 and sun50i_h6
 205 -  Amlogic Meson S905 (GXBB)
 206 -  Arm Juno Software Development Platform
 207 -  Arm Neoverse N1 System Development Platform (N1SDP)
 208 -  Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
 209 -  Arm Neoverse Reference Design E1 Edge (RD-E1-Edge) FVP
 210 -  Arm SGI-575 and SGM-775
 211 -  Arm Versatile Express FVP
 212 -  HiKey, HiKey960 and Poplar boards
 213 -  Intel Stratix 10 SoC FPGA
 214 -  Marvell Armada 3700 and 8K
 215 -  MediaTek MT6795 and MT8173 SoCs
 216 -  NVIDIA T132, T186 and T210 SoCs
 217 -  NXP QorIQ LS1043A, i.MX8MM, i.MX8MQ, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
 218 -  QEMU
 219 -  Raspberry Pi 3
 220 -  Renesas R-Car Generation 3
 221 -  RockChip RK3328, RK3368 and RK3399 SoCs
 222 -  Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
 223 -  STMicroelectronics STM32MP1
 224 -  Texas Instruments K3 SoCs
 225 -  Xilinx Versal and Zynq UltraScale + MPSoC
 226
 227 Still to come
 228 -------------
 229
 230 -  Support for additional platforms.
 231
 232 -  Refinements to Position Independent Executable (PIE) support.
 233
 234 -  Refinements to the SPCI-based SPM implementation as the draft SPCI and SPRT
 235    specifications continue to evolve.
 236
 237 -  Documentation enhancements.
 238
 239 -  Ongoing support for new architectural features, CPUs and System IP.
 240
 241 -  Ongoing support for new Arm system architecture specifications.
 242
 243 -  Ongoing security hardening, optimization and quality improvements.
 244
 245 For a full list of detailed issues in the current code, please see the
 246 :ref:`Change Log & Release Notes` and the `issue tracker`_.
 247
 248 Getting started
 249 ---------------
 250
 251 See the :ref:`User Guide` for instructions on how to download, install, build
 252 and use TF-A with the Arm `FVP`_\ s.
 253
 254 See the :ref:`Firmware Design` for information on how TF-A works.
 255
 256 See the :ref:`Porting Guide` as well for information about how to use this
 257 software on another Armv7-A or Armv8-A platform.
 258
 259 See the :ref:`Contributor's Guide` for information on how to contribute to this
 260 project and the :ref:`Contributor Acknowledgements` file for a list of
 261 contributors to the project.
 262
 263 Contact Us
 264 ~~~~~~~~~~
 265
 266 We welcome any feedback on TF-A. If you think you have found a security
 267 vulnerability, please report this using the process defined in the TF-A
 268 :ref:`Security Handling` document.
 269
 270 For all other feedback, please use the `issue tracker`_ or our `mailing list`_.
 271
 272 Arm licensees may contact Arm directly via their partner managers.
 273
 274 --------------
 275
 276 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
 277
 278 .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
 279 .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
 280 .. _Power State Coordination Interface (PSCI): PSCI_
 281 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
 282 .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
 283 .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf
 284 .. _System Control and Management Interface (SCMI): SCMI_
 285 .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
 286 .. _Software Delegated Exception Interface (SDEI): SDEI_
 287 .. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
 288 .. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
 289 .. _Arm FVP website: FVP_
 290 .. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
 291 .. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
 292 .. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
 293 .. _NVIDIA Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
 294 .. _Trusty Secure OS: https://source.android.com/security/trusty
 295 .. _trustedfirmware.org: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
 296 .. _issue tracker: https://issues.trustedfirmware.org
 297 .. _mailing list: https://lists.trustedfirmware.org/mailman/listinfo/tf-a