bl32/sp_min/aarch32/entrypoint.S

   1 /*
   2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <asm_macros.S>
   9 #include <common/bl_common.h>
  10 #include <common/runtime_svc.h>
  11 #include <context.h>
  12 #include <el3_common_macros.S>
  13 #include <lib/xlat_tables/xlat_tables_defs.h>
  14 #include <smccc_helpers.h>
  15 #include <smccc_macros.S>
  16
  17         .globl  sp_min_vector_table
  18         .globl  sp_min_entrypoint
  19         .globl  sp_min_warm_entrypoint
  20         .globl  sp_min_handle_smc
  21         .globl  sp_min_handle_fiq
  22
  23         .macro route_fiq_to_sp_min reg
  24                 /* -----------------------------------------------------
  25                  * FIQs are secure interrupts trapped by Monitor and non
  26                  * secure is not allowed to mask the FIQs.
  27                  * -----------------------------------------------------
  28                  */
  29                 ldcopr  \reg, SCR
  30                 orr     \reg, \reg, #SCR_FIQ_BIT
  31                 bic     \reg, \reg, #SCR_FW_BIT
  32                 stcopr  \reg, SCR
  33         .endm
  34
  35         .macro clrex_on_monitor_entry
  36 #if (ARM_ARCH_MAJOR == 7)
  37         /*
  38          * ARMv7 architectures need to clear the exclusive access when
  39          * entering Monitor mode.
  40          */
  41         clrex
  42 #endif
  43         .endm
  44
  45 vector_base sp_min_vector_table
  46         b       sp_min_entrypoint
  47         b       plat_panic_handler      /* Undef */
  48         b       sp_min_handle_smc       /* Syscall */
  49         b       plat_panic_handler      /* Prefetch abort */
  50         b       plat_panic_handler      /* Data abort */
  51         b       plat_panic_handler      /* Reserved */
  52         b       plat_panic_handler      /* IRQ */
  53         b       sp_min_handle_fiq       /* FIQ */
  54
  55
  56 /*
  57  * The Cold boot/Reset entrypoint for SP_MIN
  58  */
  59 func sp_min_entrypoint
  60 #if !RESET_TO_SP_MIN
  61         /* ---------------------------------------------------------------
  62          * Preceding bootloader has populated r0 with a pointer to a
  63          * 'bl_params_t' structure & r1 with a pointer to platform
  64          * specific structure
  65          * ---------------------------------------------------------------
  66          */
  67         mov     r9, r0
  68         mov     r10, r1
  69         mov     r11, r2
  70         mov     r12, r3
  71
  72         /* ---------------------------------------------------------------------
  73          * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
  74          * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
  75          * and primary/secondary CPU logic should not be executed in this case.
  76          *
  77          * Also, assume that the previous bootloader has already initialised the
  78          * SCTLR, including the CPU endianness, and has initialised the memory.
  79          * ---------------------------------------------------------------------
  80          */
  81         el3_entrypoint_common                                   \
  82                 _init_sctlr=0                                   \
  83                 _warm_boot_mailbox=0                            \
  84                 _secondary_cold_boot=0                          \
  85                 _init_memory=0                                  \
  86                 _init_c_runtime=1                               \
  87                 _exception_vectors=sp_min_vector_table
  88
  89         /* ---------------------------------------------------------------------
  90          * Relay the previous bootloader's arguments to the platform layer
  91          * ---------------------------------------------------------------------
  92          */
  93 #else
  94         /* ---------------------------------------------------------------------
  95          * For RESET_TO_SP_MIN systems which have a programmable reset address,
  96          * sp_min_entrypoint() is executed only on the cold boot path so we can
  97          * skip the warm boot mailbox mechanism.
  98          * ---------------------------------------------------------------------
  99          */
 100         el3_entrypoint_common                                   \
 101                 _init_sctlr=1                                   \
 102                 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS  \
 103                 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU      \
 104                 _init_memory=1                                  \
 105                 _init_c_runtime=1                               \
 106                 _exception_vectors=sp_min_vector_table
 107
 108         /* ---------------------------------------------------------------------
 109          * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
 110          * to run so there's no argument to relay from a previous bootloader.
 111          * Zero the arguments passed to the platform layer to reflect that.
 112          * ---------------------------------------------------------------------
 113          */
 114         mov     r9, #0
 115         mov     r10, #0
 116         mov     r11, #0
 117         mov     r12, #0
 118
 119 #endif /* RESET_TO_SP_MIN */
 120
 121 #if SP_MIN_WITH_SECURE_FIQ
 122         route_fiq_to_sp_min r4
 123 #endif
 124
 125         mov     r0, r9
 126         mov     r1, r10
 127         mov     r2, r11
 128         mov     r3, r12
 129         bl      sp_min_early_platform_setup2
 130         bl      sp_min_plat_arch_setup
 131
 132         /* Jump to the main function */
 133         bl      sp_min_main
 134
 135         /* -------------------------------------------------------------
 136          * Clean the .data & .bss sections to main memory. This ensures
 137          * that any global data which was initialised by the primary CPU
 138          * is visible to secondary CPUs before they enable their data
 139          * caches and participate in coherency.
 140          * -------------------------------------------------------------
 141          */
 142         ldr     r0, =__DATA_START__
 143         ldr     r1, =__DATA_END__
 144         sub     r1, r1, r0
 145         bl      clean_dcache_range
 146
 147         ldr     r0, =__BSS_START__
 148         ldr     r1, =__BSS_END__
 149         sub     r1, r1, r0
 150         bl      clean_dcache_range
 151
 152         bl      smc_get_next_ctx
 153
 154         /* r0 points to `smc_ctx_t` */
 155         /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
 156         /* BRCM_PATCH: PMCR passed from boot loader needs to be saved to initial ATF context.
 157          *             Othewise, PMCR setting will be lost, when ATF returns to next stage boot loader.
 158          */
 159         push    {r1}
 160         ldcopr  r1, PMCR
 161         str     r1, [r0, #SMC_CTX_PMCR]
 162         pop     {r1}
 163         b       sp_min_exit
 164 endfunc sp_min_entrypoint
 165
 166
 167 /*
 168  * SMC handling function for SP_MIN.
 169  */
 170 func sp_min_handle_smc
 171         /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
 172         str     lr, [sp, #SMC_CTX_LR_MON]
 173
 174         smccc_save_gp_mode_regs
 175
 176         clrex_on_monitor_entry
 177
 178         /*
 179          * `sp` still points to `smc_ctx_t`. Save it to a register
 180          * and restore the C runtime stack pointer to `sp`.
 181          */
 182         mov     r2, sp                          /* handle */
 183         ldr     sp, [r2, #SMC_CTX_SP_MON]
 184
 185         ldr     r0, [r2, #SMC_CTX_SCR]
 186         and     r3, r0, #SCR_NS_BIT             /* flags */
 187
 188         /* Switch to Secure Mode*/
 189         bic     r0, #SCR_NS_BIT
 190         stcopr  r0, SCR
 191         isb
 192
 193         ldr     r0, [r2, #SMC_CTX_GPREG_R0]     /* smc_fid */
 194         /* Check whether an SMC64 is issued */
 195         tst     r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
 196         beq     1f
 197         /* SMC32 is not detected. Return error back to caller */
 198         mov     r0, #SMC_UNK
 199         str     r0, [r2, #SMC_CTX_GPREG_R0]
 200         mov     r0, r2
 201         b       sp_min_exit
 202 1:
 203         /* SMC32 is detected */
 204         mov     r1, #0                          /* cookie */
 205         bl      handle_runtime_svc
 206
 207         /* `r0` points to `smc_ctx_t` */
 208         b       sp_min_exit
 209 endfunc sp_min_handle_smc
 210
 211 /*
 212  * Secure Interrupts handling function for SP_MIN.
 213  */
 214 func sp_min_handle_fiq
 215 #if !SP_MIN_WITH_SECURE_FIQ
 216         b plat_panic_handler
 217 #else
 218         /* FIQ has a +4 offset for lr compared to preferred return address */
 219         sub     lr, lr, #4
 220         /* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
 221         str     lr, [sp, #SMC_CTX_LR_MON]
 222
 223         smccc_save_gp_mode_regs
 224
 225         clrex_on_monitor_entry
 226
 227         /* load run-time stack */
 228         mov     r2, sp
 229         ldr     sp, [r2, #SMC_CTX_SP_MON]
 230
 231         /* Switch to Secure Mode */
 232         ldr     r0, [r2, #SMC_CTX_SCR]
 233         bic     r0, #SCR_NS_BIT
 234         stcopr  r0, SCR
 235         isb
 236
 237         push    {r2, r3}
 238         bl      sp_min_fiq
 239         pop     {r0, r3}
 240
 241         b       sp_min_exit
 242 #endif
 243 endfunc sp_min_handle_fiq
 244
 245 /*
 246  * The Warm boot entrypoint for SP_MIN.
 247  */
 248 func sp_min_warm_entrypoint
 249         /*
 250          * On the warm boot path, most of the EL3 initialisations performed by
 251          * 'el3_entrypoint_common' must be skipped:
 252          *
 253          *  - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
 254          *    programming the reset address do we need to initialied the SCTLR.
 255          *    In other cases, we assume this has been taken care by the
 256          *    entrypoint code.
 257          *
 258          *  - No need to determine the type of boot, we know it is a warm boot.
 259          *
 260          *  - Do not try to distinguish between primary and secondary CPUs, this
 261          *    notion only exists for a cold boot.
 262          *
 263          *  - No need to initialise the memory or the C runtime environment,
 264          *    it has been done once and for all on the cold boot path.
 265          */
 266         el3_entrypoint_common                                   \
 267                 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS          \
 268                 _warm_boot_mailbox=0                            \
 269                 _secondary_cold_boot=0                          \
 270                 _init_memory=0                                  \
 271                 _init_c_runtime=0                               \
 272                 _exception_vectors=sp_min_vector_table
 273
 274         /*
 275          * We're about to enable MMU and participate in PSCI state coordination.
 276          *
 277          * The PSCI implementation invokes platform routines that enable CPUs to
 278          * participate in coherency. On a system where CPUs are not
 279          * cache-coherent without appropriate platform specific programming,
 280          * having caches enabled until such time might lead to coherency issues
 281          * (resulting from stale data getting speculatively fetched, among
 282          * others). Therefore we keep data caches disabled even after enabling
 283          * the MMU for such platforms.
 284          *
 285          * On systems with hardware-assisted coherency, or on single cluster
 286          * platforms, such platform specific programming is not required to
 287          * enter coherency (as CPUs already are); and there's no reason to have
 288          * caches disabled either.
 289          */
 290 #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
 291         mov     r0, #0
 292 #else
 293         mov     r0, #DISABLE_DCACHE
 294 #endif
 295         /* BRCM_PATCH: BCM63138 (Cortex-A9) does not support long MMU descriptor.
 296          *             Need to use A9 specific short MMU descriptor.
 297          */
 298 #if defined(PLATFORM_FLAVOR_63138)
 299         bl      a9_l1cache_inval_d
 300         bl      a9_bl32_plat_enable_mmu
 301 #else
 302         bl      bl32_plat_enable_mmu
 303 #endif
 304
 305 #if SP_MIN_WITH_SECURE_FIQ
 306         route_fiq_to_sp_min r0
 307 #endif
 308
 309 #if defined(SPD_opteed)
 310         bl opteed_setup
 311 #endif
 312
 313         bl      sp_min_warm_boot
 314         bl      smc_get_next_ctx
 315         /* r0 points to `smc_ctx_t` */
 316         /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
 317         b       sp_min_exit
 318 endfunc sp_min_warm_entrypoint
 319
 320 /*
 321  * The function to restore the registers from SMC context and return
 322  * to the mode restored to SPSR.
 323  *
 324  * Arguments : r0 must point to the SMC context to restore from.
 325  */
 326 func sp_min_exit
 327         monitor_exit
 328 endfunc sp_min_exit