bl31/aarch64/bl31_entrypoint.S

   1 /*
   2  * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8
   9 #include <arch.h>
  10 #include <common/bl_common.h>
  11 #include <el3_common_macros.S>
  12 #include <lib/pmf/pmf_asm_macros.S>
  13 #include <lib/runtime_instr.h>
  14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
  15 #include <context.h>
  16
  17         .globl  bl31_entrypoint
  18         .globl  bl31_warm_entrypoint
  19
  20         /* -----------------------------------------------------
  21          * bl31_entrypoint() is the cold boot entrypoint,
  22          * executed only by the primary cpu.
  23          * -----------------------------------------------------
  24          */
  25
  26 func bl31_entrypoint
  27         /* ---------------------------------------------------------------
  28          * Stash the previous bootloader arguments x0 - x3 for later use.
  29          * ---------------------------------------------------------------
  30          */
  31         mov     x20, x0
  32         mov     x21, x1
  33         mov     x22, x2
  34         mov     x23, x3
  35
  36         /* --------------------------------------------------------------------
  37          * If PIE is enabled, fixup the Global descriptor Table and dynamic
  38          * relocations
  39          * --------------------------------------------------------------------
  40          */
  41 #if ENABLE_PIE
  42         mov_imm x0, BL31_BASE
  43         mov_imm x1, BL31_LIMIT
  44         bl      fixup_gdt_reloc
  45 #endif /* ENABLE_PIE */
  46
  47 #if !RESET_TO_BL31
  48         /* ---------------------------------------------------------------------
  49          * For !RESET_TO_BL31 systems, only the primary CPU ever reaches
  50          * bl31_entrypoint() during the cold boot flow, so the cold/warm boot
  51          * and primary/secondary CPU logic should not be executed in this case.
  52          *
  53          * Also, assume that the previous bootloader has already initialised the
  54          * SCTLR_EL3, including the endianness, and has initialised the memory.
  55          * ---------------------------------------------------------------------
  56          */
  57         el3_entrypoint_common                                   \
  58                 _init_sctlr=0                                   \
  59                 _warm_boot_mailbox=0                            \
  60                 _secondary_cold_boot=0                          \
  61                 _init_memory=0                                  \
  62                 _init_c_runtime=1                               \
  63                 _exception_vectors=runtime_exceptions
  64 #else
  65
  66         /* ---------------------------------------------------------------------
  67          * For RESET_TO_BL31 systems which have a programmable reset address,
  68          * bl31_entrypoint() is executed only on the cold boot path so we can
  69          * skip the warm boot mailbox mechanism.
  70          * ---------------------------------------------------------------------
  71          */
  72         el3_entrypoint_common                                   \
  73                 _init_sctlr=1                                   \
  74                 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS  \
  75                 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU      \
  76                 _init_memory=1                                  \
  77                 _init_c_runtime=1                               \
  78                 _exception_vectors=runtime_exceptions
  79
  80         /* ---------------------------------------------------------------------
  81          * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
  82          * there's no argument to relay from a previous bootloader. Zero the
  83          * arguments passed to the platform layer to reflect that.
  84          * ---------------------------------------------------------------------
  85          */
  86         mov     x20, 0
  87         mov     x21, 0
  88         mov     x22, 0
  89         mov     x23, 0
  90 #endif /* RESET_TO_BL31 */
  91
  92         /* --------------------------------------------------------------------
  93          * Perform BL31 setup
  94          * --------------------------------------------------------------------
  95          */
  96         mov     x0, x20
  97         mov     x1, x21
  98         mov     x2, x22
  99         mov     x3, x23
 100         bl      bl31_setup
 101
 102 #if ENABLE_PAUTH
 103         /* --------------------------------------------------------------------
 104          * Program APIAKey_EL1 and enable pointer authentication
 105          * --------------------------------------------------------------------
 106          */
 107         bl      pauth_init_enable_el3
 108 #endif /* ENABLE_PAUTH */
 109
 110         /* --------------------------------------------------------------------
 111          * Jump to main function
 112          * --------------------------------------------------------------------
 113          */
 114         bl      bl31_main
 115
 116         /* --------------------------------------------------------------------
 117          * Clean the .data & .bss sections to main memory. This ensures
 118          * that any global data which was initialised by the primary CPU
 119          * is visible to secondary CPUs before they enable their data
 120          * caches and participate in coherency.
 121          * --------------------------------------------------------------------
 122          */
 123         adr     x0, __DATA_START__
 124         adr     x1, __DATA_END__
 125         sub     x1, x1, x0
 126         bl      clean_dcache_range
 127
 128         adr     x0, __BSS_START__
 129         adr     x1, __BSS_END__
 130         sub     x1, x1, x0
 131         bl      clean_dcache_range
 132
 133 /* BRCM_PATCH: Save the CTX_PMCR_EL0 configured by boot loader
 134 */
 135         msr     spsel, #MODE_SP_ELX
 136         mrs     x17, pmcr_el0
 137         str     x17, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
 138         msr     spsel, #MODE_SP_EL0
 139
 140         b       el3_exit
 141 endfunc bl31_entrypoint
 142
 143         /* --------------------------------------------------------------------
 144          * This CPU has been physically powered up. It is either resuming from
 145          * suspend or has simply been turned on. In both cases, call the BL31
 146          * warmboot entrypoint
 147          * --------------------------------------------------------------------
 148          */
 149         .align 8
 150 func bl31_warm_entrypoint
 151 #if ENABLE_RUNTIME_INSTRUMENTATION
 152
 153         /*
 154          * This timestamp update happens with cache off.  The next
 155          * timestamp collection will need to do cache maintenance prior
 156          * to timestamp update.
 157          */
 158         pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
 159         mrs     x1, cntpct_el0
 160         str     x1, [x0]
 161 #endif
 162
 163         /*
 164          * On the warm boot path, most of the EL3 initialisations performed by
 165          * 'el3_entrypoint_common' must be skipped:
 166          *
 167          *  - Only when the platform bypasses the BL1/BL31 entrypoint by
 168          *    programming the reset address do we need to initialise SCTLR_EL3.
 169          *    In other cases, we assume this has been taken care by the
 170          *    entrypoint code.
 171          *
 172          *  - No need to determine the type of boot, we know it is a warm boot.
 173          *
 174          *  - Do not try to distinguish between primary and secondary CPUs, this
 175          *    notion only exists for a cold boot.
 176          *
 177          *  - No need to initialise the memory or the C runtime environment,
 178          *    it has been done once and for all on the cold boot path.
 179          */
 180         el3_entrypoint_common                                   \
 181                 _init_sctlr=PROGRAMMABLE_RESET_ADDRESS          \
 182                 _warm_boot_mailbox=0                            \
 183                 _secondary_cold_boot=0                          \
 184                 _init_memory=0                                  \
 185                 _init_c_runtime=0                               \
 186                 _exception_vectors=runtime_exceptions
 187
 188         /*
 189          * We're about to enable MMU and participate in PSCI state coordination.
 190          *
 191          * The PSCI implementation invokes platform routines that enable CPUs to
 192          * participate in coherency. On a system where CPUs are not
 193          * cache-coherent without appropriate platform specific programming,
 194          * having caches enabled until such time might lead to coherency issues
 195          * (resulting from stale data getting speculatively fetched, among
 196          * others). Therefore we keep data caches disabled even after enabling
 197          * the MMU for such platforms.
 198          *
 199          * On systems with hardware-assisted coherency, or on single cluster
 200          * platforms, such platform specific programming is not required to
 201          * enter coherency (as CPUs already are); and there's no reason to have
 202          * caches disabled either.
 203          */
 204 #if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
 205         mov     x0, xzr
 206 #else
 207         mov     x0, #DISABLE_DCACHE
 208 #endif
 209         bl      bl31_plat_enable_mmu
 210
 211 #if ENABLE_PAUTH
 212         /* --------------------------------------------------------------------
 213          * Program APIAKey_EL1 and enable pointer authentication
 214          * --------------------------------------------------------------------
 215          */
 216         bl      pauth_init_enable_el3
 217 #endif /* ENABLE_PAUTH */
 218
 219         bl      psci_warmboot_entrypoint
 220
 221 #if ENABLE_RUNTIME_INSTRUMENTATION
 222         pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
 223         mov     x19, x0
 224
 225         /*
 226          * Invalidate before updating timestamp to ensure previous timestamp
 227          * updates on the same cache line with caches disabled are properly
 228          * seen by the same core. Without the cache invalidate, the core might
 229          * write into a stale cache line.
 230          */
 231         mov     x1, #PMF_TS_SIZE
 232         mov     x20, x30
 233         bl      inv_dcache_range
 234         mov     x30, x20
 235
 236         mrs     x0, cntpct_el0
 237         str     x0, [x19]
 238 #endif
 239         b       el3_exit
 240 endfunc bl31_warm_entrypoint