Add support for Cortex-A76AE CPU

Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 769ad4505cc2455146b4de44dd5dd502bf05eb37..fe8ce5ff9384e650d363690ed7b62617692940a1 100644 (file)
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1669,6 +1669,8 @@ The FVP models used are Version 11.5 Build 33, unless otherwise stated.
 -  ``FVP_Base_Cortex-A73x4``
 -  ``FVP_Base_Cortex-A75x4``
 -  ``FVP_Base_Cortex-A76x4``
+-  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
+-  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
 -  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
 -  ``FVP_Base_Deimos``
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)

diff --git a/include/lib/cpus/aarch64/cortex_a76ae.h b/include/lib/cpus/aarch64/cortex_a76ae.h
new file mode 100644 (file)
index 0000000..9e34efb
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a76ae.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A76AE_H
+#define CORTEX_A76AE_H
+
+#include <lib/utils_def.h>
+
+/* Cortex-A76AE MIDR for revision 0 */
+#define CORTEX_A76AE_MIDR              U(0x410FD0E0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A76AE_CPUPWRCTLR_EL1    S3_0_C15_C2_7
+
+/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
+#define CORTEX_A76AE_CORE_PWRDN_EN_MASK        U(0x1)
+
+#define CORTEX_A76AE_CPUECTLR_EL1      S3_0_C15_C1_4
+
+#endif /* CORTEX_A76AE_H */

diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
new file mode 100644 (file)
index 0000000..1ba8e9a
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+#include <cortex_a76ae.h>
+#include <cpu_macros.S>
+
+       /* ---------------------------------------------
+        * HW will do the cache maintenance while powering down
+        * ---------------------------------------------
+        */
+func cortex_a76ae_core_pwr_dwn
+       /* ---------------------------------------------
+        * Enable CPU power down bit in power control register
+        * ---------------------------------------------
+        */
+       mrs     x0, CORTEX_A76AE_CPUPWRCTLR_EL1
+       orr     x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
+       msr     CORTEX_A76AE_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc cortex_a76ae_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A76AE. Must follow AAPCS.
+ */
+func cortex_a76ae_errata_report
+       ret
+endfunc cortex_a76ae_errata_report
+#endif /* REPORT_ERRATA */
+
+       /* ---------------------------------------------
+        * This function provides cortex_a76ae specific
+        * register information for crash reporting.
+        * It needs to return with x6 pointing to
+        * a list of register names in ascii and
+        * x8 - x15 having values of registers to be
+        * reported.
+        * ---------------------------------------------
+        */
+.section .rodata.cortex_a76ae_regs, "aS"
+cortex_a76ae_regs:  /* The ASCII list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func cortex_a76ae_cpu_reg_dump
+       adr     x6, cortex_a76ae_regs
+       mrs     x8, CORTEX_A76AE_CPUECTLR_EL1
+       ret
+endfunc cortex_a76ae_cpu_reg_dump
+
+declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \
+       cortex_a76ae_core_pwr_dwn

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 61a3734ffddc1379a0f2710c73158f2cf928d7e9..1a63e874c9d1ecd3559e9ee13e10e2bdd600abd7 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -103,6 +103,7 @@ FVP_CPU_LIBS                +=      lib/cpus/aarch64/cortex_a35.S                   \
                                lib/cpus/aarch64/cortex_a73.S                   \
                                lib/cpus/aarch64/cortex_a75.S                   \
                                lib/cpus/aarch64/cortex_a76.S                   \
+                               lib/cpus/aarch64/cortex_a76ae.S                 \
                                lib/cpus/aarch64/neoverse_n1.S                  \
                                lib/cpus/aarch64/cortex_deimos.S                \
                                lib/cpus/aarch64/neoverse_zeus.S

diff --git a/readme.rst b/readme.rst
index 849bbb3b99d838193f4c986f37cec2f7552df22e..d7260d7a3bbc069334dde342579f3b40121cc28d 100644 (file)
--- a/readme.rst
+++ b/readme.rst
@@ -185,6 +185,8 @@ The FVP models used are Version 11.5 Build 33, unless otherwise stated.
 -  ``FVP_Base_Cortex-A73x4``
 -  ``FVP_Base_Cortex-A75x4``
 -  ``FVP_Base_Cortex-A76x4``
+-  ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
+-  ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
 -  ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
 -  ``FVP_Base_Deimos``
 -  ``FVP_CSS_SGI-575`` (Version 11.3 build 42)