TPL is at SRAM while other stage is at SDRAM, so it needs
separate STACK.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_NEEDS_SEPARATE_TEXT_BASE
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_NEEDS_SEPARATE_TEXT_BASE
+ imply TPL_NEEDS_SEPARATE_STACK
imply TPL_OF_CONTROL
imply TPL_OF_PLATDATA
imply TPL_RAM
imply TPL_OF_CONTROL
imply TPL_OF_PLATDATA
imply TPL_RAM
config TPL_MAX_SIZE
default 32768
config TPL_MAX_SIZE
default 32768
+config TPL_STACK
+ default 0xff718000
+
endif
config ROCKCHIP_RK3328
endif
config ROCKCHIP_RK3328