rockchip: dts: rk3288: move reloc tag into -u-boot dts
[project/bcm63xx/u-boot.git] / arch / arm / dts / rk3288.dtsi
index 487d22c9b012aeae73a4afc2240f76e6d9e981bf..866fc08215245eab36ad8bcdc30c459362361fd8 100644 (file)
        };
 
        dmc: dmc@ff610000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-dmc", "syscon";
                rockchip,cru = <&cru>;
                rockchip,grf = <&grf>;
        };
 
        pmu: power-management@ff730000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-pmu", "syscon";
                reg = <0xff730000 0x100>;
        };
 
        sgrf: syscon@ff740000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-sgrf", "syscon";
                reg = <0xff740000 0x1000>;
        };
                compatible = "rockchip,rk3288-cru";
                reg = <0xff760000 0x1000>;
                rockchip,grf = <&grf>;
-               u-boot,dm-pre-reloc;
                #clock-cells = <1>;
                #reset-cells = <1>;
                assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
        };
 
        grf: syscon@ff770000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-grf", "syscon";
                reg = <0xff770000 0x1000>;
        };
        };
 
        vopb: vop@ff930000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-vop";
                reg = <0xff930000 0x19c>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                iommus = <&vopl_mmu>;
                power-domains = <&power RK3288_PD_VIO>;
                status = "disabled";
-               u-boot,dm-pre-reloc;
                vopl_out: port {
                        #address-cells = <1>;
                        #size-cells = <0>;
        };
 
        noc: syscon@ffac0000 {
-               u-boot,dm-pre-reloc;
                compatible = "rockchip,rk3288-noc", "syscon";
                reg = <0xffac0000 0x2000>;
        };