toolchain/binutils/patches/2.40/034-bpf-fix-error-conversion-from-long-unsigned-int-to-u.patch

   1 From 3e888977f165594cf44dbe8f67e3a4960b22c11f Mon Sep 17 00:00:00 2001
   2 From: "Guillermo E. Martinez" <guillermo.e.martinez@oracle.com>
   3 Date: Fri, 3 Feb 2023 11:17:49 -0600
   4 Subject: [PATCH 34/50] bpf: fix error conversion from long unsigned int to
   5  unsigned int [-Werror=overflow]
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Regenerating BPF target using the maintainer mode emits:
  11 .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow]
  12   57 |   64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  13
  14 The use of a narrow size to handle the mask CGEN in instruction format
  15 is causing this error.  Additionally eBPF `call' instructions
  16 constructed by expressions using symbols (BPF_PSEUDO_CALL) emits
  17 annotations in `src' field of the instruction, used to identify BPF
  18 target endianness.
  19
  20 cpu/
  21         * bpf.cpu (define-call-insn): Remove `src' field from
  22         instruction mask.
  23
  24 include/
  25         *opcode/cge.h (CGEN_IFMT): Adjust mask bit width.
  26
  27 opcodes/
  28         * bpf-opc.c: Regenerate.
  29
  30 (cherry picked from commit 7f6ebecd56e690012b05af0a492280765b17f186)
  31 ---
  32  cpu/bpf.cpu           |  2 +-
  33  include/opcode/cgen.h |  2 +-
  34  opcodes/bpf-opc.c     | 54 +++++++++++++++++++++++--------------------
  35  opcodes/cgen-dis.c    |  2 +-
  36  4 files changed, 32 insertions(+), 28 deletions(-)
  37
  38 --- a/cpu/bpf.cpu
  39 +++ b/cpu/bpf.cpu
  40 @@ -768,7 +768,7 @@
  41         "call"
  42         (endian-isas x-endian)
  43         "call $disp32"
  44 -       (+ disp32 (f-offset16 0) (f-regs 0)
  45 +       (+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0)
  46            OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
  47         (c-call VOID
  48                 "bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
  49 --- a/include/opcode/cgen.h
  50 +++ b/include/opcode/cgen.h
  51 @@ -914,7 +914,7 @@ typedef struct
  52       Each insn's value is stored with the insn.
  53       The first step in recognizing an insn for disassembly is
  54       (opcode & mask) == value.  */
  55 -  CGEN_INSN_INT mask;
  56 +  CGEN_INSN_LGUINT mask;
  57  #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask)
  58
  59    /* Instruction fields.
  60 --- a/opcodes/bpf-opc.c
  61 +++ b/opcodes/bpf-opc.c
  62 @@ -50,99 +50,103 @@ static const CGEN_IFMT ifmt_empty ATTRIB
  63  };
  64
  65  static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
  66 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  67 +  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  68  };
  69
  70  static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
  71 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  72 +  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  73  };
  74
  75  static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
  76 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  77 +  64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  78  };
  79
  80  static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
  81 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  82 +  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  83  };
  84
  85  static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
  86 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  87 +  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  88  };
  89
  90  static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
  91 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  92 +  64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  93  };
  94
  95  static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
  96 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  97 +  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
  98  };
  99
 100  static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
 101 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 102 +  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 103  };
 104
 105  static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
 106 -  64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 107 +  64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 108  };
 109
 110  static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
 111 -  64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 112 +  64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 113  };
 114
 115  static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
 116 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
 117 +  64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
 118  };
 119
 120  static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
 121 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 122 +  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 123  };
 124
 125  static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
 126 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 127 +  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 128  };
 129
 130  static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
 131 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 132 +  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 133  };
 134
 135  static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
 136 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 137 +  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 138  };
 139
 140  static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
 141 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 142 +  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 143  };
 144
 145  static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
 146 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 147 +  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 148  };
 149
 150  static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
 151 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 152 +  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 153  };
 154
 155  static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
 156 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 157 +  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 158  };
 159
 160  static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
 161 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 162 +  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 163  };
 164
 165  static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
 166 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 167 +  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 168  };
 169
 170  static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
 171 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 172 +  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 173 +};
 174 +
 175 +static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {
 176 +  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 177  };
 178
 179  static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
 180 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 181 +  64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 182  };
 183
 184  static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
 185 -  64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 186 +  64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
 187  };
 188
 189  #undef F
 190 @@ -1646,7 +1650,7 @@ static const CGEN_OPCODE bpf_cgen_insn_o
 191    {
 192      { 0, 0, 0, 0 },
 193      { { MNEM, ' ', OP (DISP32), 0 } },
 194 -    & ifmt_callle, { 0x85 }
 195 +    & ifmt_callbe, { 0x85 }
 196    },
 197  /* call $dstle */
 198    {
 199 --- a/opcodes/cgen-dis.c
 200 +++ b/opcodes/cgen-dis.c
 201 @@ -39,7 +39,7 @@ static void            add_insn_to_hash_chain (CG
 202  static int
 203  count_decodable_bits (const CGEN_INSN *insn)
 204  {
 205 -  unsigned mask = CGEN_INSN_BASE_MASK (insn);
 206 +  CGEN_INSN_LGUINT mask = CGEN_INSN_BASE_MASK (insn);
 207  #if GCC_VERSION >= 3004
 208    return __builtin_popcount (mask);
 209  #else