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realtek: remove unused FDB print routing
[openwrt/staging/zorun.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / common.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9 extern struct rtl83xx_soc_info soc_info;
10
11 extern const struct rtl838x_reg rtl838x_reg;
12 extern const struct rtl838x_reg rtl839x_reg;
13 extern const struct rtl838x_reg rtl930x_reg;
14 extern const struct rtl838x_reg rtl931x_reg;
15
16 extern const struct dsa_switch_ops rtl83xx_switch_ops;
17 extern const struct dsa_switch_ops rtl930x_switch_ops;
18
19 DEFINE_MUTEX(smi_lock);
20
21 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
22 {
23 u32 msti = 0;
24 u32 port_state[4];
25 int index, bit;
26 int pos = port;
27 int n = priv->port_width << 1;
28
29 /* Ports above or equal CPU port can never be configured */
30 if (port >= priv->cpu_port)
31 return -1;
32
33 mutex_lock(&priv->reg_mutex);
34
35 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
36 if (priv->family_id == RTL8390_FAMILY_ID)
37 pos += 12;
38 if (priv->family_id == RTL9300_FAMILY_ID)
39 pos += 3;
40 if (priv->family_id == RTL9310_FAMILY_ID)
41 pos += 8;
42
43 index = n - (pos >> 4) - 1;
44 bit = (pos << 1) % 32;
45
46 priv->r->stp_get(priv, msti, port_state);
47
48 mutex_unlock(&priv->reg_mutex);
49
50 return (port_state[index] >> bit) & 3;
51 }
52
53 static struct table_reg rtl838x_tbl_regs[] = {
54 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
55 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
56 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
57
58 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
59 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
60 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
61 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
62
63 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
64 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
65 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
66 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
67 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
68 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
69
70 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
71 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
72 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
73 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
74 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
75 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
76 };
77
78 void rtl_table_init(void)
79 {
80 int i;
81
82 for (i = 0; i < RTL_TBL_END; i++)
83 mutex_init(&rtl838x_tbl_regs[i].lock);
84 }
85
86 /*
87 * Request access to table t in table access register r
88 * Returns a handle to a lock for that table
89 */
90 struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
91 {
92 if (r >= RTL_TBL_END)
93 return NULL;
94
95 if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
96 return NULL;
97
98 mutex_lock(&rtl838x_tbl_regs[r].lock);
99 rtl838x_tbl_regs[r].tbl = t;
100
101 return &rtl838x_tbl_regs[r];
102 }
103
104 /*
105 * Release a table r, unlock the corresponding lock
106 */
107 void rtl_table_release(struct table_reg *r)
108 {
109 if (!r)
110 return;
111
112 // pr_info("Unlocking %08x\n", (u32)r);
113 mutex_unlock(&r->lock);
114 // pr_info("Unlock done\n");
115 }
116
117 /*
118 * Reads table index idx into the data registers of the table
119 */
120 void rtl_table_read(struct table_reg *r, int idx)
121 {
122 u32 cmd = r->rmode ? BIT(r->c_bit) : 0;
123
124 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
125 sw_w32(cmd, r->addr);
126 pr_debug("Writing %08x to %x for read\n", cmd, r->addr);
127 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
128 }
129
130 /*
131 * Writes the content of the table data registers into the table at index idx
132 */
133 void rtl_table_write(struct table_reg *r, int idx)
134 {
135 u32 cmd = r->rmode ? 0 : BIT(r->c_bit);
136
137 cmd |= BIT(r->c_bit + 1) | (r->tbl << r->t_bit) | (idx & (BIT(r->t_bit) - 1));
138 pr_debug("Writing %08x to %x for write, value %08x\n",
139 cmd, r->addr, sw_r32(0xb344));
140 sw_w32(cmd, r->addr);
141 do { } while (sw_r32(r->addr) & BIT(r->c_bit + 1));
142 }
143
144 /*
145 * Returns the address of the ith data register of table register r
146 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
147 */
148 inline u16 rtl_table_data(struct table_reg *r, int i)
149 {
150 if (i >= r->max_data)
151 i = r->max_data - 1;
152 return r->data + i * 4;
153 }
154
155 inline u32 rtl_table_data_r(struct table_reg *r, int i)
156 {
157 return sw_r32(rtl_table_data(r, i));
158 }
159
160 inline void rtl_table_data_w(struct table_reg *r, u32 v, int i)
161 {
162 sw_w32(v, rtl_table_data(r, i));
163 }
164
165 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
166 void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
167 {
168 sw_w32_mask((u32)clear, (u32)set, reg);
169 }
170
171 void rtl838x_set_port_reg(u64 set, int reg)
172 {
173 sw_w32((u32)set, reg);
174 }
175
176 u64 rtl838x_get_port_reg(int reg)
177 {
178 return ((u64) sw_r32(reg));
179 }
180
181 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
182 void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
183 {
184 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
185 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
186 }
187
188 u64 rtl839x_get_port_reg_be(int reg)
189 {
190 u64 v = sw_r32(reg);
191
192 v <<= 32;
193 v |= sw_r32(reg + 4);
194 return v;
195 }
196
197 void rtl839x_set_port_reg_be(u64 set, int reg)
198 {
199 sw_w32(set >> 32, reg);
200 sw_w32(set & 0xffffffff, reg + 4);
201 }
202
203 void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
204 {
205 sw_w32_mask((u32)clear, (u32)set, reg);
206 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
207 }
208
209 void rtl839x_set_port_reg_le(u64 set, int reg)
210 {
211 sw_w32(set, reg);
212 sw_w32(set >> 32, reg + 4);
213 }
214
215 u64 rtl839x_get_port_reg_le(int reg)
216 {
217 u64 v = sw_r32(reg + 4);
218
219 v <<= 32;
220 v |= sw_r32(reg);
221 return v;
222 }
223
224 int read_phy(u32 port, u32 page, u32 reg, u32 *val)
225 {
226 switch (soc_info.family) {
227 case RTL8380_FAMILY_ID:
228 return rtl838x_read_phy(port, page, reg, val);
229 case RTL8390_FAMILY_ID:
230 return rtl839x_read_phy(port, page, reg, val);
231 case RTL9300_FAMILY_ID:
232 return rtl930x_read_phy(port, page, reg, val);
233 case RTL9310_FAMILY_ID:
234 return rtl931x_read_phy(port, page, reg, val);
235 }
236 return -1;
237 }
238
239 int write_phy(u32 port, u32 page, u32 reg, u32 val)
240 {
241 switch (soc_info.family) {
242 case RTL8380_FAMILY_ID:
243 return rtl838x_write_phy(port, page, reg, val);
244 case RTL8390_FAMILY_ID:
245 return rtl839x_write_phy(port, page, reg, val);
246 case RTL9300_FAMILY_ID:
247 return rtl930x_write_phy(port, page, reg, val);
248 case RTL9310_FAMILY_ID:
249 return rtl931x_write_phy(port, page, reg, val);
250 }
251 return -1;
252 }
253
254 static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
255 {
256 struct device *dev = priv->dev;
257 struct device_node *dn, *mii_np = dev->of_node;
258 struct mii_bus *bus;
259 int ret;
260 u32 pn;
261
262 pr_debug("In %s\n", __func__);
263 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
264 if (mii_np) {
265 pr_debug("Found compatible MDIO node!\n");
266 } else {
267 dev_err(priv->dev, "no %s child node found", "mdio-bus");
268 return -ENODEV;
269 }
270
271 priv->mii_bus = of_mdio_find_bus(mii_np);
272 if (!priv->mii_bus) {
273 pr_debug("Deferring probe of mdio bus\n");
274 return -EPROBE_DEFER;
275 }
276 if (!of_device_is_available(mii_np))
277 ret = -ENODEV;
278
279 bus = devm_mdiobus_alloc(priv->ds->dev);
280 if (!bus)
281 return -ENOMEM;
282
283 bus->name = "rtl838x slave mii";
284
285 /*
286 * Since the NIC driver is loaded first, we can use the mdio rw functions
287 * assigned there.
288 */
289 bus->read = priv->mii_bus->read;
290 bus->write = priv->mii_bus->write;
291 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
292
293 bus->parent = dev;
294 priv->ds->slave_mii_bus = bus;
295 priv->ds->slave_mii_bus->priv = priv;
296
297 ret = mdiobus_register(priv->ds->slave_mii_bus);
298 if (ret && mii_np) {
299 of_node_put(dn);
300 return ret;
301 }
302
303 dn = mii_np;
304 for_each_node_by_name(dn, "ethernet-phy") {
305 if (of_property_read_u32(dn, "reg", &pn))
306 continue;
307
308 priv->ports[pn].dp = dsa_to_port(priv->ds, pn);
309
310 // Check for the integrated SerDes of the RTL8380M first
311 if (of_property_read_bool(dn, "phy-is-integrated")
312 && priv->id == 0x8380 && pn >= 24) {
313 pr_debug("----> FÓUND A SERDES\n");
314 priv->ports[pn].phy = PHY_RTL838X_SDS;
315 continue;
316 }
317
318 if (of_property_read_bool(dn, "phy-is-integrated")
319 && !of_property_read_bool(dn, "sfp")) {
320 priv->ports[pn].phy = PHY_RTL8218B_INT;
321 continue;
322 }
323
324 if (!of_property_read_bool(dn, "phy-is-integrated")
325 && of_property_read_bool(dn, "sfp")) {
326 priv->ports[pn].phy = PHY_RTL8214FC;
327 continue;
328 }
329
330 if (!of_property_read_bool(dn, "phy-is-integrated")
331 && !of_property_read_bool(dn, "sfp")) {
332 priv->ports[pn].phy = PHY_RTL8218B_EXT;
333 continue;
334 }
335 }
336
337 // TODO: Do this needs to come from the .dts, at least the SerDes number
338 if (priv->family_id == RTL9300_FAMILY_ID) {
339 priv->ports[24].is2G5 = true;
340 priv->ports[25].is2G5 = true;
341 priv->ports[24].sds_num = 1;
342 priv->ports[24].sds_num = 2;
343 }
344
345 /* Disable MAC polling the PHY so that we can start configuration */
346 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
347
348 /* Enable PHY control via SoC */
349 if (priv->family_id == RTL8380_FAMILY_ID) {
350 /* Enable SerDes NWAY and PHY control via SoC */
351 sw_w32_mask(BIT(7), BIT(15), RTL838X_SMI_GLB_CTRL);
352 } else {
353 /* Disable PHY polling via SoC */
354 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
355 }
356
357 /* Power on fibre ports and reset them if necessary */
358 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
359 pr_debug("Powering on fibre ports & reset\n");
360 rtl8380_sds_power(24, 1);
361 rtl8380_sds_power(26, 1);
362 }
363
364 // TODO: Only power on SerDes with external PHYs connected
365 if (priv->family_id == RTL9300_FAMILY_ID) {
366 pr_info("RTL9300 Powering on SerDes ports\n");
367 rtl9300_sds_power(24, 1);
368 rtl9300_sds_power(25, 1);
369 rtl9300_sds_power(26, 1);
370 rtl9300_sds_power(27, 1);
371 }
372
373 pr_debug("%s done\n", __func__);
374 return 0;
375 }
376
377 static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv)
378 {
379 int t = sw_r32(priv->r->l2_ctrl_1);
380
381 t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
382
383 if (priv->family_id == RTL8380_FAMILY_ID)
384 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
385 else
386 t = (t * 3) / 5;
387
388 pr_debug("L2 AGING time: %d sec\n", t);
389 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out));
390 return t;
391 }
392
393 /* Caller must hold priv->reg_mutex */
394 int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port)
395 {
396 struct rtl838x_switch_priv *priv = ds->priv;
397 int i;
398
399 pr_info("%s: Adding port %d to LA-group %d\n", __func__, port, group);
400 if (group >= priv->n_lags) {
401 pr_err("Link Agrregation group too large.\n");
402 return -EINVAL;
403 }
404
405 if (port >= priv->cpu_port) {
406 pr_err("Invalid port number.\n");
407 return -EINVAL;
408 }
409
410 for (i = 0; i < priv->n_lags; i++) {
411 if (priv->lags_port_members[i] & BIT_ULL(i))
412 break;
413 }
414 if (i != priv->n_lags) {
415 pr_err("%s: Port already member of LAG: %d\n", __func__, i);
416 return -ENOSPC;
417 }
418
419 priv->r->mask_port_reg_be(0, BIT_ULL(port), priv->r->trk_mbr_ctr(group));
420 priv->lags_port_members[group] |= BIT_ULL(port);
421
422 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
423 return 0;
424 }
425
426 /* Caller must hold priv->reg_mutex */
427 int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port)
428 {
429 struct rtl838x_switch_priv *priv = ds->priv;
430
431 pr_info("%s: Removing port %d from LA-group %d\n", __func__, port, group);
432
433 if (group >= priv->n_lags) {
434 pr_err("Link Agrregation group too large.\n");
435 return -EINVAL;
436 }
437
438 if (port >= priv->cpu_port) {
439 pr_err("Invalid port number.\n");
440 return -EINVAL;
441 }
442
443
444 if (!(priv->lags_port_members[group] & BIT_ULL(port))) {
445 pr_err("%s: Port not member of LAG: %d\n", __func__, group
446 );
447 return -ENOSPC;
448 }
449
450 priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->trk_mbr_ctr(group));
451 priv->lags_port_members[group] &= ~BIT_ULL(port);
452
453 pr_info("lags_port_members %d now %016llx\n", group, priv->lags_port_members[group]);
454 return 0;
455 }
456
457 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv *priv,
458 struct net_device *ndev,
459 struct netdev_notifier_changeupper_info *info)
460 {
461 struct net_device *upper = info->upper_dev;
462 int i, j, err;
463
464 if (!netif_is_lag_master(upper))
465 return 0;
466
467 mutex_lock(&priv->reg_mutex);
468
469 for (i = 0; i < priv->n_lags; i++) {
470 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == upper))
471 break;
472 }
473 for (j = 0; j < priv->cpu_port; j++) {
474 if (priv->ports[j].dp->slave == ndev)
475 break;
476 }
477 if (j >= priv->cpu_port) {
478 err = -EINVAL;
479 goto out;
480 }
481
482 if (info->linking) {
483 if (!priv->lag_devs[i])
484 priv->lag_devs[i] = upper;
485 err = rtl83xx_lag_add(priv->ds, i, priv->ports[j].dp->index);
486 if (err) {
487 err = -EINVAL;
488 goto out;
489 }
490 } else {
491 if (!priv->lag_devs[i])
492 err = -EINVAL;
493 err = rtl83xx_lag_del(priv->ds, i, priv->ports[j].dp->index);
494 if (err) {
495 err = -EINVAL;
496 goto out;
497 }
498 if (!priv->lags_port_members[i])
499 priv->lag_devs[i] = NULL;
500 }
501
502 out:
503 mutex_unlock(&priv->reg_mutex);
504 return 0;
505 }
506
507 static int rtl83xx_netdevice_event(struct notifier_block *this,
508 unsigned long event, void *ptr)
509 {
510 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
511 struct rtl838x_switch_priv *priv;
512 int err;
513
514 pr_debug("In: %s, event: %lu\n", __func__, event);
515
516 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
517 return NOTIFY_DONE;
518
519 priv = container_of(this, struct rtl838x_switch_priv, nb);
520 switch (event) {
521 case NETDEV_CHANGEUPPER:
522 err = rtl83xx_handle_changeupper(priv, ndev, ptr);
523 break;
524 }
525
526 if (err)
527 return err;
528
529 return NOTIFY_DONE;
530 }
531
532 static int __init rtl83xx_sw_probe(struct platform_device *pdev)
533 {
534 int err = 0, i;
535 struct rtl838x_switch_priv *priv;
536 struct device *dev = &pdev->dev;
537 u64 bpdu_mask;
538
539 pr_debug("Probing RTL838X switch device\n");
540 if (!pdev->dev.of_node) {
541 dev_err(dev, "No DT found\n");
542 return -EINVAL;
543 }
544
545 // Initialize access to RTL switch tables
546 rtl_table_init();
547
548 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
549 if (!priv)
550 return -ENOMEM;
551
552 priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
553
554 if (!priv->ds)
555 return -ENOMEM;
556 priv->ds->dev = dev;
557 priv->ds->priv = priv;
558 priv->ds->ops = &rtl83xx_switch_ops;
559 priv->dev = dev;
560
561 priv->family_id = soc_info.family;
562 priv->id = soc_info.id;
563 switch(soc_info.family) {
564 case RTL8380_FAMILY_ID:
565 priv->ds->ops = &rtl83xx_switch_ops;
566 priv->cpu_port = RTL838X_CPU_PORT;
567 priv->port_mask = 0x1f;
568 priv->port_width = 1;
569 priv->irq_mask = 0x0FFFFFFF;
570 priv->r = &rtl838x_reg;
571 priv->ds->num_ports = 29;
572 priv->fib_entries = 8192;
573 rtl8380_get_version(priv);
574 priv->n_lags = 8;
575 break;
576 case RTL8390_FAMILY_ID:
577 priv->ds->ops = &rtl83xx_switch_ops;
578 priv->cpu_port = RTL839X_CPU_PORT;
579 priv->port_mask = 0x3f;
580 priv->port_width = 2;
581 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
582 priv->r = &rtl839x_reg;
583 priv->ds->num_ports = 53;
584 priv->fib_entries = 16384;
585 rtl8390_get_version(priv);
586 priv->n_lags = 16;
587 break;
588 case RTL9300_FAMILY_ID:
589 priv->ds->ops = &rtl930x_switch_ops;
590 priv->cpu_port = RTL930X_CPU_PORT;
591 priv->port_mask = 0x1f;
592 priv->port_width = 1;
593 priv->irq_mask = 0x0FFFFFFF;
594 priv->r = &rtl930x_reg;
595 priv->ds->num_ports = 29;
596 priv->fib_entries = 16384;
597 priv->version = RTL8390_VERSION_A;
598 priv->n_lags = 16;
599 sw_w32(1, RTL930X_ST_CTRL);
600 break;
601 case RTL9310_FAMILY_ID:
602 priv->ds->ops = &rtl930x_switch_ops;
603 priv->cpu_port = RTL931X_CPU_PORT;
604 priv->port_mask = 0x3f;
605 priv->port_width = 2;
606 priv->irq_mask = 0xFFFFFFFFFFFFFULL;
607 priv->r = &rtl931x_reg;
608 priv->ds->num_ports = 57;
609 priv->fib_entries = 16384;
610 priv->version = RTL8390_VERSION_A;
611 priv->n_lags = 16;
612 break;
613 }
614 pr_debug("Chip version %c\n", priv->version);
615
616 err = rtl83xx_mdio_probe(priv);
617 if (err) {
618 /* Probing fails the 1st time because of missing ethernet driver
619 * initialization. Use this to disable traffic in case the bootloader left if on
620 */
621 return err;
622 }
623 err = dsa_register_switch(priv->ds);
624 if (err) {
625 dev_err(dev, "Error registering switch: %d\n", err);
626 return err;
627 }
628
629 /* Enable link and media change interrupts. Are the SERDES masks needed? */
630 sw_w32_mask(0, 3, priv->r->isr_glb_src);
631
632 priv->r->set_port_reg_le(priv->irq_mask, priv->r->isr_port_link_sts_chg);
633 priv->r->set_port_reg_le(priv->irq_mask, priv->r->imr_port_link_sts_chg);
634
635 priv->link_state_irq = platform_get_irq(pdev, 0);
636 pr_info("LINK state irq: %d\n", priv->link_state_irq);
637 switch (priv->family_id) {
638 case RTL8380_FAMILY_ID:
639 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
640 IRQF_SHARED, "rtl838x-link-state", priv->ds);
641 break;
642 case RTL8390_FAMILY_ID:
643 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
644 IRQF_SHARED, "rtl839x-link-state", priv->ds);
645 break;
646 case RTL9300_FAMILY_ID:
647 err = request_irq(priv->link_state_irq, rtl930x_switch_irq,
648 IRQF_SHARED, "rtl930x-link-state", priv->ds);
649 break;
650 case RTL9310_FAMILY_ID:
651 err = request_irq(priv->link_state_irq, rtl931x_switch_irq,
652 IRQF_SHARED, "rtl931x-link-state", priv->ds);
653 break;
654 }
655 if (err) {
656 dev_err(dev, "Error setting up switch interrupt.\n");
657 /* Need to free allocated switch here */
658 }
659
660 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
661 if (soc_info.family != RTL9310_FAMILY_ID)
662 sw_w32(0x1, priv->r->imr_glb);
663
664 rtl83xx_get_l2aging(priv);
665
666 rtl83xx_setup_qos(priv);
667
668 /* Clear all destination ports for mirror groups */
669 for (i = 0; i < 4; i++)
670 priv->mirror_group_ports[i] = -1;
671
672 priv->nb.notifier_call = rtl83xx_netdevice_event;
673 if (register_netdevice_notifier(&priv->nb)) {
674 priv->nb.notifier_call = NULL;
675 dev_err(dev, "Failed to register LAG netdev notifier\n");
676 }
677
678 // Flood BPDUs to all ports including cpu-port
679 if (soc_info.family != RTL9300_FAMILY_ID) { // TODO: Port this functionality
680 bpdu_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
681 priv->r->set_port_reg_be(bpdu_mask, priv->r->rma_bpdu_fld_pmask);
682
683 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
684 sw_w32(7, priv->r->spcl_trap_eapol_ctrl);
685
686 rtl838x_dbgfs_init(priv);
687 }
688
689 return err;
690 }
691
692 static int rtl83xx_sw_remove(struct platform_device *pdev)
693 {
694 // TODO:
695 pr_debug("Removing platform driver for rtl83xx-sw\n");
696 return 0;
697 }
698
699 static const struct of_device_id rtl83xx_switch_of_ids[] = {
700 { .compatible = "realtek,rtl83xx-switch"},
701 { /* sentinel */ }
702 };
703
704
705 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
706
707 static struct platform_driver rtl83xx_switch_driver = {
708 .probe = rtl83xx_sw_probe,
709 .remove = rtl83xx_sw_remove,
710 .driver = {
711 .name = "rtl83xx-switch",
712 .pm = NULL,
713 .of_match_table = rtl83xx_switch_of_ids,
714 },
715 };
716
717 module_platform_driver(rtl83xx_switch_driver);
718
719 MODULE_AUTHOR("B. Koblitz");
720 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
721 MODULE_LICENSE("GPL");
Staging tree of Baptiste Jonglez