target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch

   1 From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sun, 7 Feb 2021 16:52:56 +0100
   4 Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
   5
   6 Some flag are missing from the original code.
   7 These clk can't be set using the protected-clock proprities as they
   8 cause the malfunction of the serial interface.
   9 These clks are needed for the rpm interface to work proprely or the
  10 cpu regulators starts to fail as soon as they are disabled by the
  11 kernel.
  12
  13 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  14 ---
  15  drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
  16  1 file changed, 13 insertions(+), 6 deletions(-)
  17
  18 --- a/drivers/clk/qcom/gcc-ipq806x.c
  19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  20 @@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
  21                 .parent_names = (const char *[]){ "pxo" },
  22                 .num_parents = 1,
  23                 .ops = &clk_pll_ops,
  24 +               .flags = CLK_IS_CRITICAL,
  25         },
  26  };
  27
  28 @@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
  29                         .parent_names = gcc_pxo_pll8,
  30                         .num_parents = 2,
  31                         .ops = &clk_rcg_ops,
  32 -                       .flags = CLK_SET_PARENT_GATE,
  33 +                       .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
  34                 },
  35         },
  36  };
  37 @@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =
  38                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
  39                         .num_parents = 1,
  40                         .ops = &clk_branch_ops,
  41 -                       .flags = CLK_SET_RATE_PARENT,
  42 +                       .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
  43                 },
  44         },
  45  };
  46 @@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
  47                         .parent_names = gcc_pxo_pll8,
  48                         .num_parents = 2,
  49                         .ops = &clk_rcg_ops,
  50 -                       .flags = CLK_SET_PARENT_GATE,
  51 +                       .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
  52                 },
  53         },
  54  };
  55 @@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =
  56                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
  57                         .num_parents = 1,
  58                         .ops = &clk_branch_ops,
  59 -                       .flags = CLK_SET_RATE_PARENT,
  60 +                       .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
  61                 },
  62         },
  63  };
  64 @@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
  65                 .hw.init = &(struct clk_init_data){
  66                         .name = "gsbi4_h_clk",
  67                         .ops = &clk_branch_ops,
  68 +                       .flags = CLK_IGNORE_UNUSED,
  69                 },
  70         },
  71  };
  72 @@ -1293,6 +1295,7 @@ static struct clk_rcg sdc1_src = {
  73                         .parent_names = gcc_pxo_pll8,
  74                         .num_parents = 2,
  75                         .ops = &clk_rcg_ops,
  76 +                       .flags = CLK_SET_RATE_GATE,
  77                 },
  78         }
  79  };
  80 @@ -1341,6 +1344,7 @@ static struct clk_rcg sdc3_src = {
  81                         .parent_names = gcc_pxo_pll8,
  82                         .num_parents = 2,
  83                         .ops = &clk_rcg_ops,
  84 +                       .flags = CLK_SET_RATE_GATE,
  85                 },
  86         }
  87  };
  88 @@ -1424,6 +1428,7 @@ static struct clk_rcg tsif_ref_src = {
  89                         .parent_names = gcc_pxo_pll8,
  90                         .num_parents = 2,
  91                         .ops = &clk_rcg_ops,
  92 +                       .flags = CLK_SET_RATE_GATE,
  93                 },
  94         }
  95  };
  96 @@ -2694,7 +2699,8 @@ static struct clk_dyn_rcg ubi32_core1_sr
  97                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
  98                         .num_parents = 5,
  99                         .ops = &clk_dyn_rcg_ops,
 100 -                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 101 +                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
 102 +                                CLK_IGNORE_UNUSED,
 103                 },
 104         },
 105  };
 106 @@ -2747,7 +2753,8 @@ static struct clk_dyn_rcg ubi32_core2_sr
 107                         .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
 108                         .num_parents = 5,
 109                         .ops = &clk_dyn_rcg_ops,
 110 -                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
 111 +                       .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
 112 +                                CLK_IGNORE_UNUSED,
 113                 },
 114         },
 115  };