ipq40xx: switch default to 6.6
[openwrt/staging/blocktrron.git] / target / linux / ipq40xx / files-6.1 / arch / arm / boot / dts / qcom-ipq4019-lbr20.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 model = "Netgear LBR20";
11 compatible = "netgear,lbr20";
12
13 chosen {
14 bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
15 };
16
17 aliases {
18 led-boot = &led_backlight_white;
19 led-failsafe = &led_status_green;
20 led-running = &led_status_green;
21 led-upgrade = &led_status_red;
22 label-mac-device = &gmac;
23 };
24
25 keys {
26 compatible = "gpio-keys";
27
28 reset {
29 label = "reset";
30 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
32 };
33
34 wps {
35 label = "wps";
36 gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_WPS_BUTTON>;
38 };
39 };
40
41 leds {
42 compatible = "gpio-leds";
43
44 led_status_green: led-status-green {
45 function = LED_FUNCTION_STATUS;
46 color = <LED_COLOR_ID_GREEN>;
47 gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
48 default-state = "keep";
49 };
50
51 led_status_red: led-status-red {
52 function = LED_FUNCTION_STATUS;
53 color = <LED_COLOR_ID_RED>;
54 gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
55 };
56 };
57
58 gpio_export {
59 compatible = "gpio-export";
60 #size-cells = <0>;
61
62 lte_rst {
63 gpio-export,name = "lte_rst";
64 gpio-export,output = <1>;
65 gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
66 };
67
68 lte_pwrkey {
69 gpio-export,name = "lte_pwrkey";
70 gpio-export,output = <1>;
71 gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
72 };
73
74 lte_usb_boot {
75 gpio-export,name = "lte_usb_boot";
76 gpio-export,output = <0>;
77 gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
78 };
79
80 lte_pwm {
81 gpio-export,name = "lte_pwm";
82 gpio-export,output = <1>;
83 gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
84 };
85
86 };
87
88 soc {
89
90 tcsr@1949000 {
91 compatible = "qcom,tcsr";
92 reg = <0x1949000 0x100>;
93 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
94 };
95
96 tcsr@194b000 {
97 status = "okay";
98
99 compatible = "qcom,tcsr";
100 reg = <0x194b000 0x100>;
101 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
102 };
103
104 ess_tcsr@1953000 {
105 compatible = "qcom,tcsr";
106 reg = <0x1953000 0x1000>;
107 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
108 };
109
110 tcsr@1957000 {
111 compatible = "qcom,tcsr";
112 reg = <0x1957000 0x100>;
113 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
114 };
115
116 };
117 };
118
119 &prng {
120 status = "okay";
121 };
122
123 &mdio {
124 status = "okay";
125 pinctrl-0 = <&mdio_pins>;
126 pinctrl-names = "default";
127 };
128
129 &crypto {
130 status = "okay";
131 };
132
133 &watchdog {
134 status = "okay";
135 };
136
137 &usb2_hs_phy {
138 status = "okay";
139 };
140
141 &usb2 {
142 status = "okay";
143 };
144
145 &usb3_ss_phy {
146 status = "okay";
147 };
148
149 &usb3_hs_phy {
150 status = "okay";
151 };
152
153 &usb3 {
154 status = "okay";
155 };
156
157 &blsp_dma {
158 status = "okay";
159 };
160
161 &qpic_bam {
162 status = "okay";
163 };
164
165 &tlmm {
166 mdio_pins: mdio-pinmux {
167 mux_mdio {
168 pins = "gpio6";
169 function = "mdio";
170 bias-pull-up;
171 };
172
173 mux_mdc {
174 pins = "gpio7";
175 function = "mdc";
176 bias-pull-up;
177 };
178 };
179
180 serial_pins: serial-pinmux {
181 function = "blsp_uart0";
182 pins = "gpio16", "gpio17";
183 bias-disable;
184 };
185
186 nand_pins: nand-pins {
187 pullups {
188 pins = "gpio52", "gpio53", "gpio58", "gpio59";
189 function = "qpic";
190 bias-pull-up;
191 };
192
193 pulldowns {
194 pins = "gpio54", "gpio55", "gpio56",
195 "gpio57", "gpio60", "gpio61",
196 "gpio62", "gpio63", "gpio64",
197 "gpio65", "gpio66", "gpio67",
198 "gpio68", "gpio69";
199 function = "qpic";
200 bias-pull-down;
201 };
202 };
203 };
204
205 &nand {
206 pinctrl-0 = <&nand_pins>;
207 pinctrl-names = "default";
208 status = "okay";
209
210 nand@0 {
211 partitions {
212 compatible = "fixed-partitions";
213 #address-cells = <1>;
214 #size-cells = <1>;
215
216 partition@0 {
217 label = "0:SBL1";
218 reg = <0x00000000 0x00100000>;
219 read-only;
220 };
221
222 partition@100000 {
223 label = "0:MIBIB";
224 reg = <0x00100000 0x00100000>;
225 read-only;
226 };
227
228 partition@200000 {
229 label = "0:BOOTCONFIG";
230 reg = <0x00200000 0x00100000>;
231 read-only;
232 };
233
234 partition@300000 {
235 label = "0:QSEE";
236 reg = <0x00300000 0x00100000>;
237 read-only;
238 };
239
240 partition@400000 {
241 label = "0:QSEE_1";
242 reg = <0x00400000 0x00100000>;
243 read-only;
244 };
245
246 partition@500000 {
247 label = "0:CDT";
248 reg = <0x00500000 0x00080000>;
249 read-only;
250 };
251
252 partition@580000 {
253 label = "0:CDT_1";
254 reg = <0x00580000 0x00080000>;
255 read-only;
256 };
257
258 partition@600000 {
259 label = "0:BOOTCONFIG1";
260 reg = <0x00600000 0x00080000>;
261 read-only;
262 };
263
264 partition@680000 {
265 label = "0:APPSBLENV";
266 reg = <0x00680000 0x00080000>;
267 };
268
269 partition@700000 {
270 label = "0:APPSBL";
271 reg = <0x00700000 0x00200000>;
272 read-only;
273 };
274
275 partition@900000 {
276 label = "0:APPSBL_1";
277 reg = <0x00900000 0x00200000>;
278 read-only;
279 };
280
281 partition@b00000 {
282 label = "0:ART";
283 reg = <0x00b00000 0x00080000>;
284 read-only;
285
286 nvmem-layout {
287 compatible = "fixed-layout";
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 precal_art_1000: precal@1000 {
292 reg = <0x1000 0x2f20>;
293 };
294
295 precal_art_5000: precal@5000 {
296 reg = <0x5000 0x2f20>;
297 };
298
299 precal_art_9000: precal@9000 {
300 reg = <0x9000 0x2f20>;
301 };
302
303 };
304 };
305
306 partition@b80000 {
307 label = "0:ART.bak";
308 reg = <0x00b80000 0x00080000>;
309 read-only;
310 };
311
312 partition@c00000 {
313 label = "config";
314 reg = <0x00c00000 0x00100000>;
315 read-only;
316 };
317
318 partition@d00000 {
319 label = "boarddata1";
320 reg = <0x00d00000 0x00080000>;
321 read-only;
322
323 nvmem-layout {
324 compatible = "fixed-layout";
325 #address-cells = <1>;
326 #size-cells = <1>;
327
328 mac_address_lan: macaddr@0 {
329 compatible = "mac-base";
330 reg = <0x0 0x6>;
331 #nvmem-cell-cells = <1>;
332 };
333
334 mac_address_wan: macaddr@6 {
335 compatible = "mac-base";
336 reg = <0x6 0x6>;
337 #nvmem-cell-cells = <1>;
338 };
339
340 mac_address_wlan_5g: macaddr@c {
341 compatible = "mac-base";
342 reg = <0xc 0x6>;
343 #nvmem-cell-cells = <1>;
344 };
345
346 mac_address_wlan_2nd5g: macaddr@12 {
347 compatible = "mac-base";
348 reg = <0x12 0x6>;
349 #nvmem-cell-cells = <1>;
350 };
351
352 };
353 };
354
355 partition@d80000 {
356 label = "boarddata2";
357 reg = <0x00d80000 0x00040000>;
358 read-only;
359 };
360
361 partition@dc0000 {
362 label = "pot";
363 reg = <0x00dc0000 0x00100000>;
364 read-only;
365 };
366
367 partition@ec0000 {
368 label = "boarddata1.bak";
369 reg = <0x00ec0000 0x00080000>;
370 read-only;
371 };
372
373 partition@f40000 {
374 label = "boarddata2.bak";
375 reg = <0x00f40000 0x00040000>;
376 read-only;
377 };
378
379 partition@f80000 {
380 label = "language";
381 reg = <0x00f80000 0x00300000>;
382 read-only;
383 };
384
385 partition@1280000 {
386 label = "cert";
387 reg = <0x01280000 0x00080000>;
388 read-only;
389 };
390
391 partition@1300000 {
392 label = "ntgrdata";
393 reg = <0x01300000 0x09300000>;
394 };
395
396 partition@a600000 {
397 label = "kernel";
398 reg = <0x0a600000 0x00700000>;
399 };
400
401 partition@a9c0000 {
402 label = "ubi";
403 reg = <0x0ad00000 0x05300000>;
404 };
405
406 };
407 };
408 };
409
410 &blsp1_i2c3 {
411 status = "okay";
412
413 led-controller {
414 #address-cells = <1>;
415 #size-cells = <0>;
416 compatible = "ti,tlc59108"; /* really is tlc59208f */
417 reg = <0x27>;
418
419 led_backlight_green: led-backlight-green {
420 function = LED_FUNCTION_BACKLIGHT;
421 color = <LED_COLOR_ID_GREEN>;
422 reg = <0x0>;
423 linux,default-trigger = "default-off";
424 };
425
426 led_backlight_red: led-backlight-red {
427 function = LED_FUNCTION_BACKLIGHT;
428 color = <LED_COLOR_ID_RED>;
429 reg = <0x1>;
430 linux,default-trigger = "default-off";
431 };
432
433 led_backlight_blue: led-backlight-blue {
434 function = LED_FUNCTION_BACKLIGHT;
435 color = <LED_COLOR_ID_BLUE>;
436 reg = <0x2>;
437 linux,default-trigger = "default-off";
438 };
439
440 led_backlight_white: led-backlight-white {
441 function = LED_FUNCTION_BACKLIGHT;
442 color = <LED_COLOR_ID_WHITE>;
443 reg = <0x3>;
444 linux,default-trigger = "default-off";
445 };
446
447 };
448 };
449
450 &blsp1_uart1 {
451 status = "okay";
452 pinctrl-0 = <&serial_pins>;
453 pinctrl-names = "default";
454 };
455
456 &cryptobam {
457 status = "okay";
458 };
459
460 &gmac {
461 status = "okay";
462 nvmem-cell-names = "mac-address";
463 nvmem-cells = <&mac_address_lan 0>;
464 };
465
466 &switch {
467 status = "okay";
468 };
469
470 &swport4 {
471 status = "okay";
472 label = "lan1";
473 };
474
475 &swport5 {
476 status = "okay";
477 label = "lan2";
478 };
479
480 &pcie0 {
481 status = "okay";
482 perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
483 wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
484
485 bridge@0,0 {
486 reg = <0x00000000 0 0 0 0>;
487 #address-cells = <3>;
488 #size-cells = <2>;
489 ranges;
490
491 wifi@1,0 {
492 compatible = "qcom,ath10k";
493 status = "okay";
494 reg = <0x00010000 0 0 0 0>;
495 ieee80211-freq-limit = <5170000 5350000>;
496 nvmem-cell-names = "pre-calibration", "mac-address";
497 nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
498 qcom,ath10k-calibration-variant = "Netgear-LBR20";
499 };
500 };
501 };
502
503 &wifi0 {
504 status = "okay";
505 nvmem-cell-names = "pre-calibration", "mac-address";
506 nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
507 qcom,ath10k-calibration-variant = "Netgear-LBR20";
508 };
509
510 &wifi1 {
511 status = "okay";
512 ieee80211-freq-limit = <5470000 5815000>;
513 nvmem-cell-names = "pre-calibration", "mac-address";
514 nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
515 qcom,ath10k-calibration-variant = "Netgear-LBR20";
516 };