target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi

   1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
   2  * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  */
  17
  18 #include "qcom-ipq4019.dtsi"
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/input/input.h>
  21 #include <dt-bindings/soc/qcom,tcsr.h>
  22
  23 / {
  24         model = "Netgear EX61X0v2";
  25         compatible = "netgear,ex61x0v2";
  26
  27         soc {
  28                 rng@22000 {
  29                         status = "okay";
  30                 };
  31
  32                 mdio@90000 {
  33                         status = "okay";
  34                 };
  35
  36                 tcsr@1949000 {
  37                         compatible = "qcom,tcsr";
  38                         reg = <0x1949000 0x100>;
  39                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  40                 };
  41
  42                 ess_tcsr@1953000 {
  43                         compatible = "qcom,tcsr";
  44                         reg = <0x1953000 0x1000>;
  45                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  46                 };
  47
  48                 tcsr@1957000 {
  49                         compatible = "qcom,tcsr";
  50                         reg = <0x1957000 0x100>;
  51                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  52                 };
  53
  54                 crypto@8e3a000 {
  55                         status = "okay";
  56                 };
  57
  58                 watchdog@b017000 {
  59                         status = "okay";
  60                 };
  61         };
  62
  63         aliases {
  64                 led-boot = &power_amber;
  65                 led-failsafe = &power_amber;
  66                 led-running = &power_green;
  67                 led-upgrade = &power_amber;
  68         };
  69
  70         keys {
  71                 compatible = "gpio-keys";
  72
  73                 wps {
  74                         label = "wps";
  75                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  76                         linux,code = <KEY_WPS_BUTTON>;
  77                 };
  78
  79                 reset {
  80                         label = "reset";
  81                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  82                         linux,code = <KEY_RESTART>;
  83                 };
  84         };
  85
  86         led_spi {
  87                 compatible = "spi-gpio";
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90
  91                 sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  92                 mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  93                 num-chipselects = <0>;
  94
  95                 led_gpio: led_gpio@0 {
  96                         compatible = "fairchild,74hc595";
  97                         reg = <0>;
  98                         gpio-controller;
  99                         #gpio-cells = <2>;
 100                         registers-number = <1>;
 101                         spi-max-frequency = <1000000>;
 102                 };
 103         };
 104
 105         leds {
 106                 compatible = "gpio-leds";
 107
 108                 power_amber: power_amber {
 109                         label = "amber:power";
 110                         gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 111                 };
 112
 113                 power_green: power_green {
 114                         label = "green:power";
 115                         gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 116                 };
 117
 118                 right {
 119                         label = "blue:right";
 120                         gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 121                 };
 122
 123                 left {
 124                         label = "blue:left";
 125                         gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 126                 };
 127
 128                 client_green {
 129                         label = "green:client";
 130                         gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 131                 };
 132
 133                 client_red {
 134                         label = "red:client";
 135                         gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 136                 };
 137
 138                 router_green {
 139                         label = "green:router";
 140                         gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
 141                 };
 142
 143                 router_red {
 144                         label = "red:router";
 145                         gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 146                 };
 147
 148                 wps {
 149                         label = "green:wps";
 150                         gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 151                 };
 152         };
 153 };
 154
 155 &tlmm {
 156         serial_pins: serial_pinmux {
 157                 mux {
 158                         pins = "gpio60", "gpio61";
 159                         function = "blsp_uart0";
 160                         bias-disable;
 161                 };
 162         };
 163
 164         spi_0_pins: spi_0_pinmux {
 165                 pin {
 166                         function = "blsp_spi0";
 167                         pins = "gpio55", "gpio56", "gpio57";
 168                         drive-strength = <12>;
 169                         bias-disable;
 170                 };
 171                 pin_cs {
 172                         function = "gpio";
 173                         pins = "gpio54";
 174                         drive-strength = <2>;
 175                         bias-disable;
 176                         output-high;
 177                 };
 178         };
 179 };
 180
 181 &blsp1_spi1 {
 182         pinctrl-0 = <&spi_0_pins>;
 183         pinctrl-names = "default";
 184         status = "okay";
 185         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 186
 187         mx25l12805d@0 {
 188                 compatible = "jedec,spi-nor";
 189                 reg = <0>;
 190                 spi-max-frequency = <45000000>;
 191
 192                 partitions {
 193                         compatible = "fixed-partitions";
 194                         #address-cells = <1>;
 195                         #size-cells = <1>;
 196
 197                         partition0@0 {
 198                                 label = "SBL1";
 199                                 reg = <0x00000000 0x00040000>;
 200                                 read-only;
 201                         };
 202
 203                         partition1@40000 {
 204                                 label = "MIBIB";
 205                                 reg = <0x00040000 0x00020000>;
 206                                 read-only;
 207                         };
 208
 209                         partition2@60000 {
 210                                 label = "QSEE";
 211                                 reg = <0x00060000 0x00060000>;
 212                                 read-only;
 213                         };
 214
 215                         partition3@c0000 {
 216                                 label = "CDT";
 217                                 reg = <0x000c0000 0x00010000>;
 218                                 read-only;
 219                         };
 220
 221                         partition4@d0000 {
 222                                 label = "DDRPARAMS";
 223                                 reg = <0x000d0000 0x00010000>;
 224                                 read-only;
 225                         };
 226
 227                         partition5@E0000 {
 228                                 label = "APPSBLENV";
 229                                 reg = <0x000e0000 0x00010000>;
 230                                 read-only;
 231                         };
 232
 233                         partition6@F0000 {
 234                                 label = "APPSBL";
 235                                 reg = <0x000f0000 0x00080000>;
 236                                 read-only;
 237                         };
 238
 239                         partition7@170000 {
 240                                 label = "ART";
 241                                 reg = <0x00170000 0x00010000>;
 242                                 compatible = "nvmem-cells";
 243                                 read-only;
 244                                 #address-cells = <1>;
 245                                 #size-cells = <1>;
 246
 247                                 precal_art_1000: precal@1000 {
 248                                         reg = <0x1000 0x2f20>;
 249                                 };
 250
 251                                 precal_art_5000: precal@5000 {
 252                                         reg = <0x5000 0x2f20>;
 253                                 };
 254                         };
 255
 256                         partition8@180000 {
 257                                 label = "config";
 258                                 reg = <0x00180000 0x00010000>;
 259                                 read-only;
 260                         };
 261
 262                         partition9@190000 {
 263                                 label = "pot";
 264                                 reg = <0x00190000 0x00010000>;
 265                                 read-only;
 266                         };
 267
 268                         partition10@1a0000 {
 269                                 compatible = "nvmem-cells";
 270                                 label = "dnidata";
 271                                 reg = <0x001a0000 0x00010000>;
 272                                 read-only;
 273
 274                                 #address-cells = <1>;
 275                                 #size-cells = <1>;
 276
 277                                 macaddr_dnidata_0: macaddr@0 {
 278                                         reg = <0x0 0x6>;
 279                                 };
 280
 281                                 macaddr_dnidata_c: macaddr@c {
 282                                         reg = <0xc 0x6>;
 283                                 };
 284                         };
 285
 286                         partition11@1b0000 {
 287                                 compatible = "denx,fit";
 288                                 label = "firmware";
 289                                 reg = <0x001b0000 0x00e10000>;
 290                         };
 291
 292                         partition12@fc0000 {
 293                                 label = "language";
 294                                 reg = <0x00fc0000 0x00040000>;
 295                                 read-only;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &blsp1_uart1 {
 302         pinctrl-0 = <&serial_pins>;
 303         pinctrl-names = "default";
 304         status = "okay";
 305 };
 306
 307 &blsp_dma {
 308         status = "okay";
 309 };
 310
 311 &cryptobam {
 312         status = "okay";
 313 };
 314
 315 &wifi0 {
 316         status = "okay";
 317         nvmem-cell-names = "pre-calibration", "mac-address";
 318         nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
 319 };
 320
 321 &wifi1 {
 322         status = "okay";
 323         nvmem-cell-names = "pre-calibration", "mac-address";
 324         nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
 325 };