target/linux/d1/patches-6.1/0105-phy-allwinner-phy-sun6i-mipi-dphy-Add-a-variant-powe.patch

   1 From b953c09bde508c2edd8acd95abba8542b6cebff6 Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 7 Aug 2022 11:44:09 -0500
   4 Subject: [PATCH 105/117] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant
   5  power-on hook
   6
   7 The A100 variant uses the same values for the timing registers, and it
   8 uses the same final power-on sequence, but it needs a different analog
   9 register configuration in the middle. Support this by moving the
  10 variant-specific parts to a hook provided by the variant.
  11
  12 Signed-off-by: Samuel Holland <samuel@sholland.org>
  13 ---
  14  drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
  15  1 file changed, 35 insertions(+), 24 deletions(-)
  16
  17 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
  18 +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
  19 @@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
  20         SUN6I_DPHY_DIRECTION_RX,
  21  };
  22
  23 +struct sun6i_dphy;
  24 +
  25  struct sun6i_dphy_variant {
  26 +       void    (*tx_power_on)(struct sun6i_dphy *dphy);
  27         bool    supports_rx;
  28  };
  29
  30 @@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct p
  31         return 0;
  32  }
  33
  34 -static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
  35 +static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
  36  {
  37         u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
  38
  39 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
  40 -                    SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
  41 -
  42 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
  43 -                    SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
  44 -                    SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
  45 -                    SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
  46 -
  47 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
  48 -                    SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
  49 -                    SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
  50 -                    SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
  51 -                    SUN6I_DPHY_TX_TIME1_CLK_POST(10));
  52 -
  53 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
  54 -                    SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
  55 -
  56 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
  57 -
  58 -       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
  59 -                    SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
  60 -                    SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
  61 -
  62         regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
  63                      SUN6I_DPHY_ANA0_REG_PWS |
  64                      SUN6I_DPHY_ANA0_REG_DMPC |
  65 @@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct
  66                      SUN6I_DPHY_ANA3_EN_LDOC |
  67                      SUN6I_DPHY_ANA3_EN_LDOD);
  68         udelay(1);
  69 +}
  70 +
  71 +static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
  72 +{
  73 +       u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
  74 +
  75 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
  76 +                    SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
  77 +
  78 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
  79 +                    SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
  80 +                    SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
  81 +                    SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
  82 +
  83 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
  84 +                    SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
  85 +                    SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
  86 +                    SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
  87 +                    SUN6I_DPHY_TX_TIME1_CLK_POST(10));
  88 +
  89 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
  90 +                    SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
  91 +
  92 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
  93 +
  94 +       regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
  95 +                    SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
  96 +                    SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
  97 +
  98 +       dphy->variant->tx_power_on(dphy);
  99
 100         regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
 101                            SUN6I_DPHY_ANA3_EN_VTTC |
 102 @@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platf
 103  }
 104
 105  static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
 106 +       .tx_power_on    = sun6i_a31_mipi_dphy_tx_power_on,
 107         .supports_rx    = true,
 108  };
 109