target/linux/d1/patches-6.1/0102-dt-bindings-sun6i-a31-mipi-dphy-Add-the-A100-DPHY-va.patch

   1 From c7fa1be12bf0ef02f5557dd1d1100d25af4e34f5 Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 7 Aug 2022 11:00:12 -0500
   4 Subject: [PATCH 102/117] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
   5  variant
   6
   7 A100 features an updated DPHY, which moves PLL control inside the DPHY
   8 register space. (Previously PLL-MIPI was controlled from the CCU. This
   9 does not affect the "clocks" property because the link between PLL-MIPI
  10 and the DPHY was never represented in the devicetree.) It also requires
  11 a modified analog power-on sequence. Finally, the new DPHY adds support
  12 for operating as an LVDS PHY. D1 uses this same variant.
  13
  14 Signed-off-by: Samuel Holland <samuel@sholland.org>
  15 ---
  16  .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml           | 4 ++++
  17  1 file changed, 4 insertions(+)
  18
  19 --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
  20 +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
  21 @@ -17,9 +17,13 @@ properties:
  22    compatible:
  23      oneOf:
  24        - const: allwinner,sun6i-a31-mipi-dphy
  25 +      - const: allwinner,sun50i-a100-mipi-dphy
  26        - items:
  27            - const: allwinner,sun50i-a64-mipi-dphy
  28            - const: allwinner,sun6i-a31-mipi-dphy
  29 +      - items:
  30 +          - const: allwinner,sun20i-d1-mipi-dphy
  31 +          - const: allwinner,sun50i-a100-mipi-dphy
  32
  33    reg:
  34      maxItems: 1