target/linux/d1/patches-6.1/0043-hwspinlock-sun6i-Clarify-bank-counting-logic.patch

   1 From 7708f7471ab45039e08237b42121d0372f9216a7 Mon Sep 17 00:00:00 2001
   2 From: Samuel Holland <samuel@sholland.org>
   3 Date: Sun, 13 Jun 2021 23:42:19 -0500
   4 Subject: [PATCH 043/117] hwspinlock: sun6i: Clarify bank counting logic
   5
   6 In some of the most recent datasheets, the register definition was
   7 updated in a way that resolves the conflict here: the field is only two
   8 bits wide, and a value of "4" really means a bit pattern of "0". Correct
   9 the code to reflect this, but leave an updated comment because some
  10 datasheets still have incorrect information in them.
  11
  12 Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
  13 Signed-off-by: Samuel Holland <samuel@sholland.org>
  14 ---
  15  drivers/hwspinlock/sun6i_hwspinlock.c | 36 +++++++++++----------------
  16  1 file changed, 14 insertions(+), 22 deletions(-)
  17
  18 --- a/drivers/hwspinlock/sun6i_hwspinlock.c
  19 +++ b/drivers/hwspinlock/sun6i_hwspinlock.c
  20 @@ -129,30 +129,22 @@ static int sun6i_hwspinlock_probe(struct
  21         }
  22
  23         /*
  24 -        * bit 28 and 29 represents the hwspinlock setup
  25 +        * Bits 28 and 29 represent the number of available locks.
  26          *
  27 -        * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1
  28 -        * to 0x4 represent 32, 64, 128 and 256 locks
  29 -        * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,
  30 -        * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks
  31 -        * all the time, not a single mentioning of 64 locks
  32 -        * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not
  33 -        * correct
  34 -        * one thing have all in common, default value of the sysstatus register is 0x10000000,
  35 -        * which results in bit 28 being set
  36 -        * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account
  37 -        * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)
  38 +        * The datasheets have two conflicting interpretations for these bits:
  39 +        *   |  00 | 01 |  10 |  11 |
  40 +        *   +-----+----+-----+-----+
  41 +        *   | 256 | 32 |  64 | 128 | A80, A83T, H3, A64, A50, D1
  42 +        *   |  32 | 64 | 128 | 256 | H5, H6, R329
  43 +        * where some datasheets use "4" instead of "0" for the first column.
  44 +        *
  45 +        * Experiments shows that the first interpretation is correct, as all
  46 +        * known implementations report the value "1" and have 32 spinlocks.
  47          */
  48 -       num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
  49 -       switch (num_banks) {
  50 -       case 1 ... 4:
  51 -               priv->nlocks = 1 << (4 + num_banks);
  52 -               break;
  53 -       default:
  54 -               err = -EINVAL;
  55 -               dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
  56 -               goto bank_fail;
  57 -       }
  58 +       num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28 & 0x3;
  59 +       if (!num_banks)
  60 +               num_banks = 4;
  61 +       priv->nlocks = 1 << (4 + num_banks);
  62
  63         priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
  64                                   GFP_KERNEL);