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d1: add new target
[openwrt/staging/mans0n.git] / target / linux / d1 / patches-6.1 / 0028-riscv-dts-allwinner-Add-the-D1-SoC-base-devicetree.patch
1 From 20d565fb9324b0d2791d10cb65560eddd2ef526e Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Tue, 28 Jun 2022 23:20:33 -0500
4 Subject: [PATCH 028/117] riscv: dts: allwinner: Add the D1 SoC base devicetree
5
6 D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
7 one HiFi 4 DSP. The SoC is based on a design that additionally contained
8 a pair of Cortex A7's. For that reason, some peripherals are duplicated.
9
10 This devicetree includes all of the peripherals that already have a
11 documented binding.
12
13 Signed-off-by: Samuel Holland <samuel@sholland.org>
14 ---
15 arch/riscv/boot/dts/Makefile | 1 +
16 arch/riscv/boot/dts/allwinner/Makefile | 1 +
17 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
18 3 files changed, 902 insertions(+)
19 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
20 create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
21
22 --- a/arch/riscv/boot/dts/Makefile
23 +++ b/arch/riscv/boot/dts/Makefile
24 @@ -1,4 +1,5 @@
25 # SPDX-License-Identifier: GPL-2.0
26 +subdir-y += allwinner
27 subdir-y += sifive
28 subdir-y += starfive
29 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
30 --- /dev/null
31 +++ b/arch/riscv/boot/dts/allwinner/Makefile
32 @@ -0,0 +1 @@
33 +# SPDX-License-Identifier: GPL-2.0
34 --- /dev/null
35 +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
36 @@ -0,0 +1,900 @@
37 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
38 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
39 +
40 +#include <dt-bindings/clock/sun6i-rtc.h>
41 +#include <dt-bindings/clock/sun8i-de2.h>
42 +#include <dt-bindings/clock/sun8i-tcon-top.h>
43 +#include <dt-bindings/clock/sun20i-d1-ccu.h>
44 +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
45 +#include <dt-bindings/interrupt-controller/irq.h>
46 +#include <dt-bindings/reset/sun8i-de2.h>
47 +#include <dt-bindings/reset/sun20i-d1-ccu.h>
48 +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
49 +#include <dt-bindings/thermal/thermal.h>
50 +
51 +/ {
52 + #address-cells = <1>;
53 + #size-cells = <1>;
54 +
55 + cpus {
56 + timebase-frequency = <24000000>;
57 + #address-cells = <1>;
58 + #size-cells = <0>;
59 +
60 + cpu0: cpu@0 {
61 + compatible = "thead,c906", "riscv";
62 + device_type = "cpu";
63 + reg = <0>;
64 + clocks = <&ccu CLK_RISCV>;
65 + clock-frequency = <24000000>;
66 + d-cache-block-size = <64>;
67 + d-cache-sets = <256>;
68 + d-cache-size = <32768>;
69 + i-cache-block-size = <64>;
70 + i-cache-sets = <128>;
71 + i-cache-size = <32768>;
72 + mmu-type = "riscv,sv39";
73 + riscv,isa = "rv64imafdc";
74 + #cooling-cells = <2>;
75 +
76 + cpu0_intc: interrupt-controller {
77 + compatible = "riscv,cpu-intc";
78 + interrupt-controller;
79 + #address-cells = <0>;
80 + #interrupt-cells = <1>;
81 + };
82 + };
83 + };
84 +
85 + de: display-engine {
86 + compatible = "allwinner,sun20i-d1-display-engine";
87 + allwinner,pipelines = <&mixer0>, <&mixer1>;
88 + status = "disabled";
89 + };
90 +
91 + osc24M: osc24M-clk {
92 + compatible = "fixed-clock";
93 + clock-frequency = <24000000>;
94 + clock-output-names = "osc24M";
95 + #clock-cells = <0>;
96 + };
97 +
98 + soc {
99 + compatible = "simple-bus";
100 + ranges;
101 + interrupt-parent = <&plic>;
102 + dma-noncoherent;
103 + #address-cells = <1>;
104 + #size-cells = <1>;
105 +
106 + dsp_wdt: watchdog@1700400 {
107 + compatible = "allwinner,sun20i-d1-wdt";
108 + reg = <0x1700400 0x20>;
109 + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
110 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
111 + clock-names = "hosc", "losc";
112 + status = "reserved";
113 + };
114 +
115 + pio: pinctrl@2000000 {
116 + compatible = "allwinner,sun20i-d1-pinctrl";
117 + reg = <0x2000000 0x800>;
118 + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
119 + <87 IRQ_TYPE_LEVEL_HIGH>,
120 + <89 IRQ_TYPE_LEVEL_HIGH>,
121 + <91 IRQ_TYPE_LEVEL_HIGH>,
122 + <93 IRQ_TYPE_LEVEL_HIGH>,
123 + <95 IRQ_TYPE_LEVEL_HIGH>;
124 + clocks = <&ccu CLK_APB0>,
125 + <&osc24M>,
126 + <&rtc CLK_OSC32K>;
127 + clock-names = "apb", "hosc", "losc";
128 + gpio-controller;
129 + interrupt-controller;
130 + #gpio-cells = <3>;
131 + #interrupt-cells = <3>;
132 +
133 + /omit-if-no-ref/
134 + i2c0_pb10_pins: i2c0-pb10-pins {
135 + pins = "PB10", "PB11";
136 + function = "i2c0";
137 + };
138 +
139 + /omit-if-no-ref/
140 + i2c2_pb0_pins: i2c2-pb0-pins {
141 + pins = "PB0", "PB1";
142 + function = "i2c2";
143 + };
144 +
145 + /omit-if-no-ref/
146 + lcd_rgb666_pins: lcd-rgb666-pins {
147 + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
148 + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
149 + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
150 + "PD18", "PD19", "PD20", "PD21";
151 + function = "lcd0";
152 + };
153 +
154 + /omit-if-no-ref/
155 + mmc0_pins: mmc0-pins {
156 + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
157 + function = "mmc0";
158 + };
159 +
160 + /omit-if-no-ref/
161 + mmc1_pins: mmc1-pins {
162 + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
163 + function = "mmc1";
164 + };
165 +
166 + /omit-if-no-ref/
167 + mmc2_pins: mmc2-pins {
168 + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
169 + function = "mmc2";
170 + };
171 +
172 + /omit-if-no-ref/
173 + rgmii_pe_pins: rgmii-pe-pins {
174 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
175 + "PE5", "PE6", "PE7", "PE8", "PE9",
176 + "PE11", "PE12", "PE13", "PE14", "PE15";
177 + function = "emac";
178 + };
179 +
180 + /omit-if-no-ref/
181 + rmii_pe_pins: rmii-pe-pins {
182 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
183 + "PE5", "PE6", "PE7", "PE8", "PE9";
184 + function = "emac";
185 + };
186 +
187 + /omit-if-no-ref/
188 + uart0_pb8_pins: uart0-pb8-pins {
189 + pins = "PB8", "PB9";
190 + function = "uart0";
191 + };
192 +
193 + /omit-if-no-ref/
194 + uart1_pg6_pins: uart1-pg6-pins {
195 + pins = "PG6", "PG7";
196 + function = "uart1";
197 + };
198 +
199 + /omit-if-no-ref/
200 + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
201 + pins = "PG8", "PG9";
202 + function = "uart1";
203 + };
204 + };
205 +
206 + ccu: clock-controller@2001000 {
207 + compatible = "allwinner,sun20i-d1-ccu";
208 + reg = <0x2001000 0x1000>;
209 + clocks = <&osc24M>,
210 + <&rtc CLK_OSC32K>,
211 + <&rtc CLK_IOSC>;
212 + clock-names = "hosc", "losc", "iosc";
213 + #clock-cells = <1>;
214 + #reset-cells = <1>;
215 + };
216 +
217 + lradc: keys@2009800 {
218 + compatible = "allwinner,sun20i-d1-lradc",
219 + "allwinner,sun50i-r329-lradc";
220 + reg = <0x2009800 0x400>;
221 + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
222 + clocks = <&ccu CLK_BUS_LRADC>;
223 + resets = <&ccu RST_BUS_LRADC>;
224 + status = "disabled";
225 + };
226 +
227 + codec: audio-codec@2030000 {
228 + compatible = "simple-mfd", "syscon";
229 + reg = <0x2030000 0x1000>;
230 + #address-cells = <1>;
231 + #size-cells = <1>;
232 +
233 + regulators@2030348 {
234 + compatible = "allwinner,sun20i-d1-analog-ldos";
235 + reg = <0x2030348 0x4>;
236 + nvmem-cells = <&bg_trim>;
237 + nvmem-cell-names = "bg_trim";
238 +
239 + reg_aldo: aldo {
240 + };
241 +
242 + reg_hpldo: hpldo {
243 + };
244 + };
245 + };
246 +
247 + i2s0: i2s@2032000 {
248 + compatible = "allwinner,sun20i-d1-i2s",
249 + "allwinner,sun50i-r329-i2s";
250 + reg = <0x2032000 0x1000>;
251 + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
252 + clocks = <&ccu CLK_BUS_I2S0>,
253 + <&ccu CLK_I2S0>;
254 + clock-names = "apb", "mod";
255 + resets = <&ccu RST_BUS_I2S0>;
256 + dmas = <&dma 3>, <&dma 3>;
257 + dma-names = "rx", "tx";
258 + status = "disabled";
259 + #sound-dai-cells = <0>;
260 + };
261 +
262 + i2s1: i2s@2033000 {
263 + compatible = "allwinner,sun20i-d1-i2s",
264 + "allwinner,sun50i-r329-i2s";
265 + reg = <0x2033000 0x1000>;
266 + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
267 + clocks = <&ccu CLK_BUS_I2S1>,
268 + <&ccu CLK_I2S1>;
269 + clock-names = "apb", "mod";
270 + resets = <&ccu RST_BUS_I2S1>;
271 + dmas = <&dma 4>, <&dma 4>;
272 + dma-names = "rx", "tx";
273 + status = "disabled";
274 + #sound-dai-cells = <0>;
275 + };
276 +
277 + i2s2: i2s@2034000 {
278 + compatible = "allwinner,sun20i-d1-i2s",
279 + "allwinner,sun50i-r329-i2s";
280 + reg = <0x2034000 0x1000>;
281 + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
282 + clocks = <&ccu CLK_BUS_I2S2>,
283 + <&ccu CLK_I2S2>;
284 + clock-names = "apb", "mod";
285 + resets = <&ccu RST_BUS_I2S2>;
286 + dmas = <&dma 5>, <&dma 5>;
287 + dma-names = "rx", "tx";
288 + status = "disabled";
289 + #sound-dai-cells = <0>;
290 + };
291 +
292 + timer: timer@2050000 {
293 + compatible = "allwinner,sun20i-d1-timer",
294 + "allwinner,sun8i-a23-timer";
295 + reg = <0x2050000 0xa0>;
296 + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
297 + <76 IRQ_TYPE_LEVEL_HIGH>;
298 + clocks = <&osc24M>;
299 + };
300 +
301 + wdt: watchdog@20500a0 {
302 + compatible = "allwinner,sun20i-d1-wdt-reset",
303 + "allwinner,sun20i-d1-wdt";
304 + reg = <0x20500a0 0x20>;
305 + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
306 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
307 + clock-names = "hosc", "losc";
308 + status = "reserved";
309 + };
310 +
311 + uart0: serial@2500000 {
312 + compatible = "snps,dw-apb-uart";
313 + reg = <0x2500000 0x400>;
314 + reg-io-width = <4>;
315 + reg-shift = <2>;
316 + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
317 + clocks = <&ccu CLK_BUS_UART0>;
318 + resets = <&ccu RST_BUS_UART0>;
319 + dmas = <&dma 14>, <&dma 14>;
320 + dma-names = "rx", "tx";
321 + status = "disabled";
322 + };
323 +
324 + uart1: serial@2500400 {
325 + compatible = "snps,dw-apb-uart";
326 + reg = <0x2500400 0x400>;
327 + reg-io-width = <4>;
328 + reg-shift = <2>;
329 + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
330 + clocks = <&ccu CLK_BUS_UART1>;
331 + resets = <&ccu RST_BUS_UART1>;
332 + dmas = <&dma 15>, <&dma 15>;
333 + dma-names = "rx", "tx";
334 + status = "disabled";
335 + };
336 +
337 + uart2: serial@2500800 {
338 + compatible = "snps,dw-apb-uart";
339 + reg = <0x2500800 0x400>;
340 + reg-io-width = <4>;
341 + reg-shift = <2>;
342 + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
343 + clocks = <&ccu CLK_BUS_UART2>;
344 + resets = <&ccu RST_BUS_UART2>;
345 + dmas = <&dma 16>, <&dma 16>;
346 + dma-names = "rx", "tx";
347 + status = "disabled";
348 + };
349 +
350 + uart3: serial@2500c00 {
351 + compatible = "snps,dw-apb-uart";
352 + reg = <0x2500c00 0x400>;
353 + reg-io-width = <4>;
354 + reg-shift = <2>;
355 + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
356 + clocks = <&ccu CLK_BUS_UART3>;
357 + resets = <&ccu RST_BUS_UART3>;
358 + dmas = <&dma 17>, <&dma 17>;
359 + dma-names = "rx", "tx";
360 + status = "disabled";
361 + };
362 +
363 + uart4: serial@2501000 {
364 + compatible = "snps,dw-apb-uart";
365 + reg = <0x2501000 0x400>;
366 + reg-io-width = <4>;
367 + reg-shift = <2>;
368 + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
369 + clocks = <&ccu CLK_BUS_UART4>;
370 + resets = <&ccu RST_BUS_UART4>;
371 + dmas = <&dma 18>, <&dma 18>;
372 + dma-names = "rx", "tx";
373 + status = "disabled";
374 + };
375 +
376 + uart5: serial@2501400 {
377 + compatible = "snps,dw-apb-uart";
378 + reg = <0x2501400 0x400>;
379 + reg-io-width = <4>;
380 + reg-shift = <2>;
381 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
382 + clocks = <&ccu CLK_BUS_UART5>;
383 + resets = <&ccu RST_BUS_UART5>;
384 + dmas = <&dma 19>, <&dma 19>;
385 + dma-names = "rx", "tx";
386 + status = "disabled";
387 + };
388 +
389 + i2c0: i2c@2502000 {
390 + compatible = "allwinner,sun20i-d1-i2c",
391 + "allwinner,sun8i-v536-i2c",
392 + "allwinner,sun6i-a31-i2c";
393 + reg = <0x2502000 0x400>;
394 + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
395 + clocks = <&ccu CLK_BUS_I2C0>;
396 + resets = <&ccu RST_BUS_I2C0>;
397 + dmas = <&dma 43>, <&dma 43>;
398 + dma-names = "rx", "tx";
399 + status = "disabled";
400 + #address-cells = <1>;
401 + #size-cells = <0>;
402 + };
403 +
404 + i2c1: i2c@2502400 {
405 + compatible = "allwinner,sun20i-d1-i2c",
406 + "allwinner,sun8i-v536-i2c",
407 + "allwinner,sun6i-a31-i2c";
408 + reg = <0x2502400 0x400>;
409 + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
410 + clocks = <&ccu CLK_BUS_I2C1>;
411 + resets = <&ccu RST_BUS_I2C1>;
412 + dmas = <&dma 44>, <&dma 44>;
413 + dma-names = "rx", "tx";
414 + status = "disabled";
415 + #address-cells = <1>;
416 + #size-cells = <0>;
417 + };
418 +
419 + i2c2: i2c@2502800 {
420 + compatible = "allwinner,sun20i-d1-i2c",
421 + "allwinner,sun8i-v536-i2c",
422 + "allwinner,sun6i-a31-i2c";
423 + reg = <0x2502800 0x400>;
424 + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
425 + clocks = <&ccu CLK_BUS_I2C2>;
426 + resets = <&ccu RST_BUS_I2C2>;
427 + dmas = <&dma 45>, <&dma 45>;
428 + dma-names = "rx", "tx";
429 + status = "disabled";
430 + #address-cells = <1>;
431 + #size-cells = <0>;
432 + };
433 +
434 + i2c3: i2c@2502c00 {
435 + compatible = "allwinner,sun20i-d1-i2c",
436 + "allwinner,sun8i-v536-i2c",
437 + "allwinner,sun6i-a31-i2c";
438 + reg = <0x2502c00 0x400>;
439 + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
440 + clocks = <&ccu CLK_BUS_I2C3>;
441 + resets = <&ccu RST_BUS_I2C3>;
442 + dmas = <&dma 46>, <&dma 46>;
443 + dma-names = "rx", "tx";
444 + status = "disabled";
445 + #address-cells = <1>;
446 + #size-cells = <0>;
447 + };
448 +
449 + syscon: syscon@3000000 {
450 + compatible = "allwinner,sun20i-d1-system-control";
451 + reg = <0x3000000 0x1000>;
452 + ranges;
453 + #address-cells = <1>;
454 + #size-cells = <1>;
455 +
456 + regulators@3000150 {
457 + compatible = "allwinner,sun20i-d1-system-ldos";
458 + reg = <0x3000150 0x4>;
459 +
460 + reg_ldoa: ldoa {
461 + };
462 +
463 + reg_ldob: ldob {
464 + };
465 + };
466 + };
467 +
468 + dma: dma-controller@3002000 {
469 + compatible = "allwinner,sun20i-d1-dma";
470 + reg = <0x3002000 0x1000>;
471 + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
472 + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
473 + clock-names = "bus", "mbus";
474 + resets = <&ccu RST_BUS_DMA>;
475 + dma-channels = <16>;
476 + dma-requests = <48>;
477 + #dma-cells = <1>;
478 + };
479 +
480 + sid: efuse@3006000 {
481 + compatible = "allwinner,sun20i-d1-sid";
482 + reg = <0x3006000 0x1000>;
483 + #address-cells = <1>;
484 + #size-cells = <1>;
485 +
486 + ths_calib: ths-calib@14 {
487 + reg = <0x14 0x4>;
488 + };
489 +
490 + bg_trim: bg-trim@28 {
491 + reg = <0x28 0x4>;
492 + bits = <16 8>;
493 + };
494 + };
495 +
496 + mbus: dram-controller@3102000 {
497 + compatible = "allwinner,sun20i-d1-mbus";
498 + reg = <0x3102000 0x1000>,
499 + <0x3103000 0x1000>;
500 + reg-names = "mbus", "dram";
501 + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
502 + clocks = <&ccu CLK_MBUS>,
503 + <&ccu CLK_DRAM>,
504 + <&ccu CLK_BUS_DRAM>;
505 + clock-names = "mbus", "dram", "bus";
506 + dma-ranges = <0 0x40000000 0x80000000>;
507 + #address-cells = <1>;
508 + #size-cells = <1>;
509 + #interconnect-cells = <1>;
510 + };
511 +
512 + mmc0: mmc@4020000 {
513 + compatible = "allwinner,sun20i-d1-mmc";
514 + reg = <0x4020000 0x1000>;
515 + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
516 + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
517 + clock-names = "ahb", "mmc";
518 + resets = <&ccu RST_BUS_MMC0>;
519 + reset-names = "ahb";
520 + cap-sd-highspeed;
521 + max-frequency = <150000000>;
522 + no-mmc;
523 + status = "disabled";
524 + #address-cells = <1>;
525 + #size-cells = <0>;
526 + };
527 +
528 + mmc1: mmc@4021000 {
529 + compatible = "allwinner,sun20i-d1-mmc";
530 + reg = <0x4021000 0x1000>;
531 + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
532 + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
533 + clock-names = "ahb", "mmc";
534 + resets = <&ccu RST_BUS_MMC1>;
535 + reset-names = "ahb";
536 + cap-sd-highspeed;
537 + max-frequency = <150000000>;
538 + no-mmc;
539 + status = "disabled";
540 + #address-cells = <1>;
541 + #size-cells = <0>;
542 + };
543 +
544 + mmc2: mmc@4022000 {
545 + compatible = "allwinner,sun20i-d1-emmc",
546 + "allwinner,sun50i-a100-emmc";
547 + reg = <0x4022000 0x1000>;
548 + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
549 + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
550 + clock-names = "ahb", "mmc";
551 + resets = <&ccu RST_BUS_MMC2>;
552 + reset-names = "ahb";
553 + cap-mmc-highspeed;
554 + max-frequency = <150000000>;
555 + mmc-ddr-1_8v;
556 + mmc-ddr-3_3v;
557 + no-sd;
558 + no-sdio;
559 + status = "disabled";
560 + #address-cells = <1>;
561 + #size-cells = <0>;
562 + };
563 +
564 + usb_otg: usb@4100000 {
565 + compatible = "allwinner,sun20i-d1-musb",
566 + "allwinner,sun8i-a33-musb";
567 + reg = <0x4100000 0x400>;
568 + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
569 + interrupt-names = "mc";
570 + clocks = <&ccu CLK_BUS_OTG>;
571 + resets = <&ccu RST_BUS_OTG>;
572 + extcon = <&usbphy 0>;
573 + phys = <&usbphy 0>;
574 + phy-names = "usb";
575 + status = "disabled";
576 + };
577 +
578 + usbphy: phy@4100400 {
579 + compatible = "allwinner,sun20i-d1-usb-phy";
580 + reg = <0x4100400 0x100>,
581 + <0x4101800 0x100>,
582 + <0x4200800 0x100>;
583 + reg-names = "phy_ctrl",
584 + "pmu0",
585 + "pmu1";
586 + clocks = <&osc24M>,
587 + <&osc24M>;
588 + clock-names = "usb0_phy",
589 + "usb1_phy";
590 + resets = <&ccu RST_USB_PHY0>,
591 + <&ccu RST_USB_PHY1>;
592 + reset-names = "usb0_reset",
593 + "usb1_reset";
594 + status = "disabled";
595 + #phy-cells = <1>;
596 + };
597 +
598 + ehci0: usb@4101000 {
599 + compatible = "allwinner,sun20i-d1-ehci",
600 + "generic-ehci";
601 + reg = <0x4101000 0x100>;
602 + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
603 + clocks = <&ccu CLK_BUS_OHCI0>,
604 + <&ccu CLK_BUS_EHCI0>,
605 + <&ccu CLK_USB_OHCI0>;
606 + resets = <&ccu RST_BUS_OHCI0>,
607 + <&ccu RST_BUS_EHCI0>;
608 + phys = <&usbphy 0>;
609 + phy-names = "usb";
610 + status = "disabled";
611 + };
612 +
613 + ohci0: usb@4101400 {
614 + compatible = "allwinner,sun20i-d1-ohci",
615 + "generic-ohci";
616 + reg = <0x4101400 0x100>;
617 + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
618 + clocks = <&ccu CLK_BUS_OHCI0>,
619 + <&ccu CLK_USB_OHCI0>;
620 + resets = <&ccu RST_BUS_OHCI0>;
621 + phys = <&usbphy 0>;
622 + phy-names = "usb";
623 + status = "disabled";
624 + };
625 +
626 + ehci1: usb@4200000 {
627 + compatible = "allwinner,sun20i-d1-ehci",
628 + "generic-ehci";
629 + reg = <0x4200000 0x100>;
630 + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
631 + clocks = <&ccu CLK_BUS_OHCI1>,
632 + <&ccu CLK_BUS_EHCI1>,
633 + <&ccu CLK_USB_OHCI1>;
634 + resets = <&ccu RST_BUS_OHCI1>,
635 + <&ccu RST_BUS_EHCI1>;
636 + phys = <&usbphy 1>;
637 + phy-names = "usb";
638 + status = "disabled";
639 + };
640 +
641 + ohci1: usb@4200400 {
642 + compatible = "allwinner,sun20i-d1-ohci",
643 + "generic-ohci";
644 + reg = <0x4200400 0x100>;
645 + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
646 + clocks = <&ccu CLK_BUS_OHCI1>,
647 + <&ccu CLK_USB_OHCI1>;
648 + resets = <&ccu RST_BUS_OHCI1>;
649 + phys = <&usbphy 1>;
650 + phy-names = "usb";
651 + status = "disabled";
652 + };
653 +
654 + emac: ethernet@4500000 {
655 + compatible = "allwinner,sun20i-d1-emac",
656 + "allwinner,sun50i-a64-emac";
657 + reg = <0x4500000 0x10000>;
658 + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
659 + interrupt-names = "macirq";
660 + clocks = <&ccu CLK_BUS_EMAC>;
661 + clock-names = "stmmaceth";
662 + resets = <&ccu RST_BUS_EMAC>;
663 + reset-names = "stmmaceth";
664 + syscon = <&syscon>;
665 + status = "disabled";
666 +
667 + mdio: mdio {
668 + compatible = "snps,dwmac-mdio";
669 + #address-cells = <1>;
670 + #size-cells = <0>;
671 + };
672 + };
673 +
674 + display_clocks: clock-controller@5000000 {
675 + compatible = "allwinner,sun20i-d1-de2-clk",
676 + "allwinner,sun50i-h5-de2-clk";
677 + reg = <0x5000000 0x10000>;
678 + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
679 + clock-names = "bus", "mod";
680 + resets = <&ccu RST_BUS_DE>;
681 + #clock-cells = <1>;
682 + #reset-cells = <1>;
683 + };
684 +
685 + mixer0: mixer@5100000 {
686 + compatible = "allwinner,sun20i-d1-de2-mixer-0";
687 + reg = <0x5100000 0x100000>;
688 + clocks = <&display_clocks CLK_BUS_MIXER0>,
689 + <&display_clocks CLK_MIXER0>;
690 + clock-names = "bus", "mod";
691 + resets = <&display_clocks RST_MIXER0>;
692 +
693 + ports {
694 + #address-cells = <1>;
695 + #size-cells = <0>;
696 +
697 + mixer0_out: port@1 {
698 + reg = <1>;
699 +
700 + mixer0_out_tcon_top_mixer0: endpoint {
701 + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
702 + };
703 + };
704 + };
705 + };
706 +
707 + mixer1: mixer@5200000 {
708 + compatible = "allwinner,sun20i-d1-de2-mixer-1";
709 + reg = <0x5200000 0x100000>;
710 + clocks = <&display_clocks CLK_BUS_MIXER1>,
711 + <&display_clocks CLK_MIXER1>;
712 + clock-names = "bus", "mod";
713 + resets = <&display_clocks RST_MIXER1>;
714 +
715 + ports {
716 + #address-cells = <1>;
717 + #size-cells = <0>;
718 +
719 + mixer1_out: port@1 {
720 + reg = <1>;
721 +
722 + mixer1_out_tcon_top_mixer1: endpoint {
723 + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
724 + };
725 + };
726 + };
727 + };
728 +
729 + tcon_top: tcon-top@5460000 {
730 + compatible = "allwinner,sun20i-d1-tcon-top";
731 + reg = <0x5460000 0x1000>;
732 + clocks = <&ccu CLK_BUS_DPSS_TOP>,
733 + <&ccu CLK_TCON_TV>,
734 + <&ccu CLK_TVE>,
735 + <&ccu CLK_TCON_LCD0>;
736 + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
737 + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
738 + resets = <&ccu RST_BUS_DPSS_TOP>;
739 + #clock-cells = <1>;
740 +
741 + ports {
742 + #address-cells = <1>;
743 + #size-cells = <0>;
744 +
745 + tcon_top_mixer0_in: port@0 {
746 + reg = <0>;
747 + #address-cells = <1>;
748 + #size-cells = <0>;
749 +
750 + tcon_top_mixer0_in_mixer0: endpoint@0 {
751 + reg = <0>;
752 + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
753 + };
754 + };
755 +
756 + tcon_top_mixer0_out: port@1 {
757 + reg = <1>;
758 + #address-cells = <1>;
759 + #size-cells = <0>;
760 +
761 + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
762 + reg = <0>;
763 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
764 + };
765 +
766 + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
767 + reg = <2>;
768 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
769 + };
770 + };
771 +
772 + tcon_top_mixer1_in: port@2 {
773 + reg = <2>;
774 + #address-cells = <1>;
775 + #size-cells = <0>;
776 +
777 + tcon_top_mixer1_in_mixer1: endpoint@1 {
778 + reg = <1>;
779 + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
780 + };
781 + };
782 +
783 + tcon_top_mixer1_out: port@3 {
784 + reg = <3>;
785 + #address-cells = <1>;
786 + #size-cells = <0>;
787 +
788 + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
789 + reg = <0>;
790 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
791 + };
792 +
793 + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
794 + reg = <2>;
795 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
796 + };
797 + };
798 +
799 + tcon_top_hdmi_in: port@4 {
800 + reg = <4>;
801 +
802 + tcon_top_hdmi_in_tcon_tv0: endpoint {
803 + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
804 + };
805 + };
806 +
807 + tcon_top_hdmi_out: port@5 {
808 + reg = <5>;
809 + };
810 + };
811 + };
812 +
813 + tcon_lcd0: lcd-controller@5461000 {
814 + compatible = "allwinner,sun20i-d1-tcon-lcd";
815 + reg = <0x5461000 0x1000>;
816 + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
817 + clocks = <&ccu CLK_BUS_TCON_LCD0>,
818 + <&ccu CLK_TCON_LCD0>;
819 + clock-names = "ahb", "tcon-ch0";
820 + clock-output-names = "tcon-pixel-clock";
821 + resets = <&ccu RST_BUS_TCON_LCD0>,
822 + <&ccu RST_BUS_LVDS0>;
823 + reset-names = "lcd", "lvds";
824 + #clock-cells = <0>;
825 +
826 + ports {
827 + #address-cells = <1>;
828 + #size-cells = <0>;
829 +
830 + tcon_lcd0_in: port@0 {
831 + reg = <0>;
832 + #address-cells = <1>;
833 + #size-cells = <0>;
834 +
835 + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
836 + reg = <0>;
837 + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
838 + };
839 +
840 + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
841 + reg = <1>;
842 + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
843 + };
844 + };
845 +
846 + tcon_lcd0_out: port@1 {
847 + reg = <1>;
848 + };
849 + };
850 + };
851 +
852 + tcon_tv0: lcd-controller@5470000 {
853 + compatible = "allwinner,sun20i-d1-tcon-tv";
854 + reg = <0x5470000 0x1000>;
855 + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
856 + clocks = <&ccu CLK_BUS_TCON_TV>,
857 + <&tcon_top CLK_TCON_TOP_TV0>;
858 + clock-names = "ahb", "tcon-ch1";
859 + resets = <&ccu RST_BUS_TCON_TV>;
860 + reset-names = "lcd";
861 +
862 + ports {
863 + #address-cells = <1>;
864 + #size-cells = <0>;
865 +
866 + tcon_tv0_in: port@0 {
867 + reg = <0>;
868 + #address-cells = <1>;
869 + #size-cells = <0>;
870 +
871 + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
872 + reg = <0>;
873 + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
874 + };
875 +
876 + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
877 + reg = <1>;
878 + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
879 + };
880 + };
881 +
882 + tcon_tv0_out: port@1 {
883 + reg = <1>;
884 +
885 + tcon_tv0_out_tcon_top_hdmi: endpoint {
886 + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
887 + };
888 + };
889 + };
890 + };
891 +
892 + riscv_wdt: watchdog@6011000 {
893 + compatible = "allwinner,sun20i-d1-wdt";
894 + reg = <0x6011000 0x20>;
895 + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
896 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
897 + clock-names = "hosc", "losc";
898 + };
899 +
900 + r_ccu: clock-controller@7010000 {
901 + compatible = "allwinner,sun20i-d1-r-ccu";
902 + reg = <0x7010000 0x400>;
903 + clocks = <&osc24M>,
904 + <&rtc CLK_OSC32K>,
905 + <&rtc CLK_IOSC>,
906 + <&ccu CLK_PLL_PERIPH0_DIV3>;
907 + clock-names = "hosc", "losc", "iosc", "pll-periph";
908 + #clock-cells = <1>;
909 + #reset-cells = <1>;
910 + };
911 +
912 + rtc: rtc@7090000 {
913 + compatible = "allwinner,sun20i-d1-rtc",
914 + "allwinner,sun50i-r329-rtc";
915 + reg = <0x7090000 0x400>;
916 + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
917 + clocks = <&r_ccu CLK_BUS_R_RTC>,
918 + <&osc24M>,
919 + <&r_ccu CLK_R_AHB>;
920 + clock-names = "bus", "hosc", "ahb";
921 + #clock-cells = <1>;
922 + };
923 +
924 + plic: interrupt-controller@10000000 {
925 + compatible = "allwinner,sun20i-d1-plic",
926 + "thead,c900-plic";
927 + reg = <0x10000000 0x4000000>;
928 + interrupts-extended = <&cpu0_intc 11>,
929 + <&cpu0_intc 9>;
930 + interrupt-controller;
931 + riscv,ndev = <176>;
932 + #address-cells = <0>;
933 + #interrupt-cells = <2>;
934 + };
935 + };
936 +};
Staging tree of Sungbo Eo