target/linux/bcm27xx/patches-5.15/950-0841-clk-tests-Add-tests-for-single-parent-mux.patch

   1 From 2ef4d6383803ef0b5b4b1efa5b7577a7970f2669 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 7 Apr 2022 14:21:55 +0200
   4 Subject: [PATCH] clk: tests: Add tests for single parent mux
   5
   6 We have a few tests for a mux with a single parent, testing the case
   7 where it used to be orphan.
   8
   9 Let's leverage most of the code but register the clock properly to test
  10 a few trivial things.
  11
  12 Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
  13 Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
  14 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  15 ---
  16  drivers/clk/clk_test.c | 186 +++++++++++++++++++++++++++++++++++++++--
  17  1 file changed, 177 insertions(+), 9 deletions(-)
  18
  19 --- a/drivers/clk/clk_test.c
  20 +++ b/drivers/clk/clk_test.c
  21 @@ -352,6 +352,181 @@ struct clk_single_parent_ctx {
  22         struct clk_hw hw;
  23  };
  24
  25 +static int clk_single_parent_mux_test_init(struct kunit *test)
  26 +{
  27 +       struct clk_single_parent_ctx *ctx;
  28 +       int ret;
  29 +
  30 +       ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
  31 +       if (!ctx)
  32 +               return -ENOMEM;
  33 +       test->priv = ctx;
  34 +
  35 +       ctx->parent_ctx.rate = DUMMY_CLOCK_INIT_RATE;
  36 +       ctx->parent_ctx.hw.init =
  37 +               CLK_HW_INIT_NO_PARENT("parent-clk",
  38 +                                     &clk_dummy_rate_ops,
  39 +                                     0);
  40 +
  41 +       ret = clk_hw_register(NULL, &ctx->parent_ctx.hw);
  42 +       if (ret)
  43 +               return ret;
  44 +
  45 +       ctx->hw.init = CLK_HW_INIT("test-clk", "parent-clk",
  46 +                                  &clk_dummy_single_parent_ops,
  47 +                                  CLK_SET_RATE_PARENT);
  48 +
  49 +       ret = clk_hw_register(NULL, &ctx->hw);
  50 +       if (ret)
  51 +               return ret;
  52 +
  53 +       return 0;
  54 +}
  55 +
  56 +static void
  57 +clk_single_parent_mux_test_exit(struct kunit *test)
  58 +{
  59 +       struct clk_single_parent_ctx *ctx = test->priv;
  60 +
  61 +       clk_hw_unregister(&ctx->hw);
  62 +       clk_hw_unregister(&ctx->parent_ctx.hw);
  63 +}
  64 +
  65 +/*
  66 + * Test that for a clock with a single parent, clk_get_parent() actually
  67 + * returns the parent.
  68 + */
  69 +static void
  70 +clk_test_single_parent_mux_get_parent(struct kunit *test)
  71 +{
  72 +       struct clk_single_parent_ctx *ctx = test->priv;
  73 +       struct clk_hw *hw = &ctx->hw;
  74 +       struct clk *clk = hw->clk;
  75 +       struct clk *parent;
  76 +
  77 +       parent = clk_get_parent(clk);
  78 +       KUNIT_EXPECT_TRUE(test, clk_is_match(parent, ctx->parent_ctx.hw.clk));
  79 +}
  80 +
  81 +/*
  82 + * Test that for a clock that can't modify its rate and with a single
  83 + * parent, if we set disjoints range on the parent and then the child,
  84 + * the second will return an error.
  85 + *
  86 + * FIXME: clk_set_rate_range() only considers the current clock when
  87 + * evaluating whether ranges are disjoints and not the upstream clocks
  88 + * ranges.
  89 + */
  90 +static void
  91 +clk_test_single_parent_mux_set_range_disjoint_child_last(struct kunit *test)
  92 +{
  93 +       struct clk_single_parent_ctx *ctx = test->priv;
  94 +       struct clk_hw *hw = &ctx->hw;
  95 +       struct clk *clk = hw->clk;
  96 +       struct clk *parent;
  97 +       int ret;
  98 +
  99 +       kunit_skip(test, "This needs to be fixed in the core.");
 100 +
 101 +       parent = clk_get_parent(clk);
 102 +       KUNIT_ASSERT_PTR_NE(test, parent, NULL);
 103 +
 104 +       ret = clk_set_rate_range(parent, 1000, 2000);
 105 +       KUNIT_ASSERT_EQ(test, ret, 0);
 106 +
 107 +       ret = clk_set_rate_range(clk, 3000, 4000);
 108 +       KUNIT_EXPECT_LT(test, ret, 0);
 109 +}
 110 +
 111 +/*
 112 + * Test that for a clock that can't modify its rate and with a single
 113 + * parent, if we set disjoints range on the child and then the parent,
 114 + * the second will return an error.
 115 + *
 116 + * FIXME: clk_set_rate_range() only considers the current clock when
 117 + * evaluating whether ranges are disjoints and not the downstream clocks
 118 + * ranges.
 119 + */
 120 +static void
 121 +clk_test_single_parent_mux_set_range_disjoint_parent_last(struct kunit *test)
 122 +{
 123 +       struct clk_single_parent_ctx *ctx = test->priv;
 124 +       struct clk_hw *hw = &ctx->hw;
 125 +       struct clk *clk = hw->clk;
 126 +       struct clk *parent;
 127 +       int ret;
 128 +
 129 +       kunit_skip(test, "This needs to be fixed in the core.");
 130 +
 131 +       parent = clk_get_parent(clk);
 132 +       KUNIT_ASSERT_PTR_NE(test, parent, NULL);
 133 +
 134 +       ret = clk_set_rate_range(clk, 1000, 2000);
 135 +       KUNIT_ASSERT_EQ(test, ret, 0);
 136 +
 137 +       ret = clk_set_rate_range(parent, 3000, 4000);
 138 +       KUNIT_EXPECT_LT(test, ret, 0);
 139 +}
 140 +
 141 +/*
 142 + * Test that for a clock that can't modify its rate and with a single
 143 + * parent, if we set a range on the parent and a more restrictive one on
 144 + * the child, and then call clk_round_rate(), the boundaries of the
 145 + * two clocks are taken into account.
 146 + */
 147 +static void
 148 +clk_test_single_parent_mux_set_range_round_rate_child_smaller(struct kunit *test)
 149 +{
 150 +       struct clk_single_parent_ctx *ctx = test->priv;
 151 +       struct clk_hw *hw = &ctx->hw;
 152 +       struct clk *clk = hw->clk;
 153 +       struct clk *parent;
 154 +       unsigned long rate;
 155 +       int ret;
 156 +
 157 +       parent = clk_get_parent(clk);
 158 +       KUNIT_ASSERT_PTR_NE(test, parent, NULL);
 159 +
 160 +       ret = clk_set_rate_range(parent, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
 161 +       KUNIT_ASSERT_EQ(test, ret, 0);
 162 +
 163 +       ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1 + 1000, DUMMY_CLOCK_RATE_2 - 1000);
 164 +       KUNIT_ASSERT_EQ(test, ret, 0);
 165 +
 166 +       rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
 167 +       KUNIT_ASSERT_GT(test, rate, 0);
 168 +       KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
 169 +       KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
 170 +
 171 +       rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000);
 172 +       KUNIT_ASSERT_GT(test, rate, 0);
 173 +       KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
 174 +       KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
 175 +}
 176 +
 177 +static struct kunit_case clk_single_parent_mux_test_cases[] = {
 178 +       KUNIT_CASE(clk_test_single_parent_mux_get_parent),
 179 +       KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_child_last),
 180 +       KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_parent_last),
 181 +       KUNIT_CASE(clk_test_single_parent_mux_set_range_round_rate_child_smaller),
 182 +       {}
 183 +};
 184 +
 185 +/*
 186 + * Test suite for a basic mux clock with one parent, with
 187 + * CLK_SET_RATE_PARENT on the child.
 188 + *
 189 + * These tests are supposed to exercise the consumer API and check that
 190 + * the state of the child and parent are sane and consistent.
 191 + */
 192 +static struct kunit_suite
 193 +clk_single_parent_mux_test_suite = {
 194 +       .name = "clk-single-parent-mux-test",
 195 +       .init = clk_single_parent_mux_test_init,
 196 +       .exit = clk_single_parent_mux_test_exit,
 197 +       .test_cases = clk_single_parent_mux_test_cases,
 198 +};
 199 +
 200  static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test)
 201  {
 202         struct clk_single_parent_ctx *ctx;
 203 @@ -388,14 +563,6 @@ static int clk_orphan_transparent_single
 204         return 0;
 205  }
 206
 207 -static void clk_orphan_transparent_single_parent_mux_test_exit(struct kunit *test)
 208 -{
 209 -       struct clk_single_parent_ctx *ctx = test->priv;
 210 -
 211 -       clk_hw_unregister(&ctx->hw);
 212 -       clk_hw_unregister(&ctx->parent_ctx.hw);
 213 -}
 214 -
 215  /*
 216   * Test that a mux-only clock, with an initial rate within a range,
 217   * will still have the same rate after the range has been enforced.
 218 @@ -440,7 +607,7 @@ static struct kunit_case clk_orphan_tran
 219  static struct kunit_suite clk_orphan_transparent_single_parent_test_suite = {
 220         .name = "clk-orphan-transparent-single-parent-test",
 221         .init = clk_orphan_transparent_single_parent_mux_test_init,
 222 -       .exit = clk_orphan_transparent_single_parent_mux_test_exit,
 223 +       .exit = clk_single_parent_mux_test_exit,
 224         .test_cases = clk_orphan_transparent_single_parent_mux_test_cases,
 225  };
 226
 227 @@ -1128,6 +1295,7 @@ kunit_test_suites(
 228         &clk_range_test_suite,
 229         &clk_range_maximize_test_suite,
 230         &clk_range_minimize_test_suite,
 231 +       &clk_single_parent_mux_test_suite,
 232         &clk_uncached_test_suite
 233  );
 234  MODULE_LICENSE("GPL v2");