target/linux/bcm27xx/patches-5.15/950-0745-overlays-Overlays-for-WaveShare-2-Chan-CAN-FD-HAT.patch

   1 From dadc749c5ccc320127871d7c3ace51a7fae479a7 Mon Sep 17 00:00:00 2001
   2 From: nmbath <mark@baggywrinkle.co.uk>
   3 Date: Thu, 24 Feb 2022 13:10:01 +0000
   4 Subject: [PATCH] overlays: Overlays for WaveShare 2-Chan CAN FD HAT
   5
   6 This patch adds the overlays for the Waveshare 2-Channel Isolated
   7 CAN FD Expansion HAT for Raspberry Pi, Multi Protections. This HAT
   8 is based on the mcp2518fd chip and can be run in two modes
   9
  10 Mode A: can0 on spi0.0 and can1 on spi1.0 (cs = pin 26)
  11 Mode B: can1 on spi0.0 and can1 in spi0.1
  12
  13 Interupts: can0 pin 25 / can1 pin 16
  14
  15 https://www.waveshare.com/2-ch-can-fd-hat.htm
  16
  17 Overlays generated by:
  18 Mode A: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false \
  19               mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
  20               mcp251xfd-overlay.dts,spi1-0,interrupt=16
  21
  22 Mode B: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 \
  23               mcp251xfd-overlay.dts,spi0-1,interrupt=16
  24 ---
  25  arch/arm/boot/dts/overlays/Makefile           |   2 +
  26  arch/arm/boot/dts/overlays/README             |  20 +++
  27  .../waveshare-can-fd-hat-mode-a-overlay.dts   | 140 ++++++++++++++++++
  28  .../waveshare-can-fd-hat-mode-b-overlay.dts   | 103 +++++++++++++
  29  4 files changed, 265 insertions(+)
  30  create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts
  31  create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts
  32
  33 --- a/arch/arm/boot/dts/overlays/Makefile
  34 +++ b/arch/arm/boot/dts/overlays/Makefile
  35 @@ -251,6 +251,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
  36         w1-gpio.dtbo \
  37         w1-gpio-pullup.dtbo \
  38         w5500.dtbo \
  39 +       waveshare-can-fd-hat-mode-a.dtbo \
  40 +       waveshare-can-fd-hat-mode-b.dtbo \
  41         wittypi.dtbo \
  42         wm8960-soundcard.dtbo
  43
  44 --- a/arch/arm/boot/dts/overlays/README
  45 +++ b/arch/arm/boot/dts/overlays/README
  46 @@ -3879,6 +3879,26 @@ Params: int_pin                 GPIO use
  47          cs                      SPI bus Chip Select (default 0)
  48
  49
  50 +Name:   waveshare-can-fd-hat-mode-a
  51 +Info:   Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT
  52 +        for Raspberry Pi, Multi Protections. Use this overlay when the
  53 +        HAT is configured in Mode A (Default), with can0 on spi0.0
  54 +        and can1 on spi1.0.
  55 +        https://www.waveshare.com/2-ch-can-fd-hat.htm
  56 +Load:   dtoverlay=waveshare-can-fd-hat-mode-a
  57 +Params: <None>
  58 +
  59 +
  60 +Name:   waveshare-can-fd-hat-mode-b
  61 +Info:   Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT
  62 +        for Raspberry Pi, Multi Protections. Use this overlay when the
  63 +        HAT is configured in Mode B (requires hardware modification), with
  64 +        can0 on spi0.0 and can1 on spi0.1.
  65 +        https://www.waveshare.com/2-ch-can-fd-hat.htm
  66 +Load:   dtoverlay=waveshare-can-fd-hat-mode-b
  67 +Params: <None>
  68 +
  69 +
  70  Name:   wittypi
  71  Info:   Configures the wittypi RTC module.
  72  Load:   dtoverlay=wittypi,<param>=<val>
  73 --- /dev/null
  74 +++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts
  75 @@ -0,0 +1,140 @@
  76 +// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=16
  77 +
  78 +// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm
  79 +// in "Mode A" (default) configuration
  80 +// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT
  81 +
  82 +/dts-v1/;
  83 +/plugin/;
  84 +
  85 +#include <dt-bindings/gpio/gpio.h>
  86 +#include <dt-bindings/interrupt-controller/irq.h>
  87 +#include <dt-bindings/pinctrl/bcm2835.h>
  88 +
  89 +/ {
  90 +       compatible = "brcm,bcm2835";
  91 +       fragment@0 {
  92 +               target = <&gpio>;
  93 +               __overlay__ {
  94 +                       spi1_pins: spi1_pins {
  95 +                               brcm,pins = <19 20 21>;
  96 +                               brcm,function = <3>;
  97 +                       };
  98 +                       spi1_cs_pins: spi1_cs_pins {
  99 +                               brcm,pins = <26>;
 100 +                               brcm,function = <1>;
 101 +                       };
 102 +               };
 103 +       };
 104 +       fragment@1 {
 105 +               target = <&spi1>;
 106 +               __overlay__ {
 107 +                       #address-cells = <1>;
 108 +                       #size-cells = <0>;
 109 +                       pinctrl-names = "default";
 110 +                       pinctrl-0 = <&spi1_pins &spi1_cs_pins>;
 111 +                       cs-gpios = <&gpio 26 1>;
 112 +                       status = "okay";
 113 +                       spidev@0 {
 114 +                               compatible = "spidev";
 115 +                               reg = <0>;
 116 +                               #address-cells = <1>;
 117 +                               #size-cells = <0>;
 118 +                               spi-max-frequency = <125000000>;
 119 +                               status = "disabled";
 120 +                       };
 121 +               };
 122 +       };
 123 +       fragment@2 {
 124 +               target = <&aux>;
 125 +               __overlay__ {
 126 +                       status = "okay";
 127 +               };
 128 +       };
 129 +       fragment@3 {
 130 +               target = <&spidev0>;
 131 +               __overlay__ {
 132 +                       status = "disabled";
 133 +               };
 134 +       };
 135 +       fragment@4 {
 136 +               target = <&gpio>;
 137 +               __overlay__ {
 138 +                       mcp251xfd_pins: mcp251xfd_spi0_0_pins {
 139 +                               brcm,pins = <25>;
 140 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 141 +                       };
 142 +               };
 143 +       };
 144 +       fragment@5 {
 145 +               target-path = "/clocks";
 146 +               __overlay__ {
 147 +                       clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
 148 +                               #clock-cells = <0>;
 149 +                               compatible = "fixed-clock";
 150 +                               clock-frequency = <40000000>;
 151 +                       };
 152 +               };
 153 +       };
 154 +       fragment@6 {
 155 +               target = <&spi0>;
 156 +               __overlay__ {
 157 +                       status = "okay";
 158 +                       #address-cells = <1>;
 159 +                       #size-cells = <0>;
 160 +                       mcp251xfd@0 {
 161 +                               compatible = "microchip,mcp251xfd";
 162 +                               reg = <0>;
 163 +                               pinctrl-names = "default";
 164 +                               pinctrl-0 = <&mcp251xfd_pins>;
 165 +                               spi-max-frequency = <20000000>;
 166 +                               interrupt-parent = <&gpio>;
 167 +                               interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
 168 +                               clocks = <&clk_mcp251xfd_osc>;
 169 +                       };
 170 +               };
 171 +       };
 172 +       fragment@7 {
 173 +               target-path = "spi1/spidev@0";
 174 +               __overlay__ {
 175 +                       status = "disabled";
 176 +               };
 177 +       };
 178 +       fragment@8 {
 179 +               target = <&gpio>;
 180 +               __overlay__ {
 181 +                       mcp251xfd_pins_1: mcp251xfd_spi1_0_pins {
 182 +                               brcm,pins = <16>;
 183 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 184 +                       };
 185 +               };
 186 +       };
 187 +       fragment@9 {
 188 +               target-path = "/clocks";
 189 +               __overlay__ {
 190 +                       clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc {
 191 +                               #clock-cells = <0>;
 192 +                               compatible = "fixed-clock";
 193 +                               clock-frequency = <40000000>;
 194 +                       };
 195 +               };
 196 +       };
 197 +       fragment@10 {
 198 +               target = <&spi1>;
 199 +               __overlay__ {
 200 +                       status = "okay";
 201 +                       #address-cells = <1>;
 202 +                       #size-cells = <0>;
 203 +                       mcp251xfd@0 {
 204 +                               compatible = "microchip,mcp251xfd";
 205 +                               reg = <0>;
 206 +                               pinctrl-names = "default";
 207 +                               pinctrl-0 = <&mcp251xfd_pins_1>;
 208 +                               spi-max-frequency = <20000000>;
 209 +                               interrupt-parent = <&gpio>;
 210 +                               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 211 +                               clocks = <&clk_mcp251xfd_osc_1>;
 212 +                       };
 213 +               };
 214 +       };
 215 +};
 216 --- /dev/null
 217 +++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts
 218 @@ -0,0 +1,103 @@
 219 +// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=16
 220 +
 221 +// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm
 222 +// in "Mode B" (requried hardware modification) configuration
 223 +// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT
 224 +
 225 +
 226 +/dts-v1/;
 227 +/plugin/;
 228 +
 229 +#include <dt-bindings/gpio/gpio.h>
 230 +#include <dt-bindings/interrupt-controller/irq.h>
 231 +#include <dt-bindings/pinctrl/bcm2835.h>
 232 +
 233 +/ {
 234 +       compatible = "brcm,bcm2835";
 235 +       fragment@0 {
 236 +               target = <&spidev0>;
 237 +               __overlay__ {
 238 +                       status = "disabled";
 239 +               };
 240 +       };
 241 +       fragment@1 {
 242 +               target = <&gpio>;
 243 +               __overlay__ {
 244 +                       mcp251xfd_pins: mcp251xfd_spi0_0_pins {
 245 +                               brcm,pins = <25>;
 246 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 247 +                       };
 248 +               };
 249 +       };
 250 +       fragment@2 {
 251 +               target-path = "/clocks";
 252 +               __overlay__ {
 253 +                       clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc {
 254 +                               #clock-cells = <0>;
 255 +                               compatible = "fixed-clock";
 256 +                               clock-frequency = <40000000>;
 257 +                       };
 258 +               };
 259 +       };
 260 +       fragment@3 {
 261 +               target = <&spi0>;
 262 +               __overlay__ {
 263 +                       status = "okay";
 264 +                       #address-cells = <1>;
 265 +                       #size-cells = <0>;
 266 +                       mcp251xfd@0 {
 267 +                               compatible = "microchip,mcp251xfd";
 268 +                               reg = <0>;
 269 +                               pinctrl-names = "default";
 270 +                               pinctrl-0 = <&mcp251xfd_pins>;
 271 +                               spi-max-frequency = <20000000>;
 272 +                               interrupt-parent = <&gpio>;
 273 +                               interrupts = <25 IRQ_TYPE_LEVEL_LOW>;
 274 +                               clocks = <&clk_mcp251xfd_osc>;
 275 +                       };
 276 +               };
 277 +       };
 278 +       fragment@4 {
 279 +               target = <&spidev1>;
 280 +               __overlay__ {
 281 +                       status = "disabled";
 282 +               };
 283 +       };
 284 +       fragment@5 {
 285 +               target = <&gpio>;
 286 +               __overlay__ {
 287 +                       mcp251xfd_pins_1: mcp251xfd_spi0_1_pins {
 288 +                               brcm,pins = <16>;
 289 +                               brcm,function = <BCM2835_FSEL_GPIO_IN>;
 290 +                       };
 291 +               };
 292 +       };
 293 +       fragment@6 {
 294 +               target-path = "/clocks";
 295 +               __overlay__ {
 296 +                       clk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc {
 297 +                               #clock-cells = <0>;
 298 +                               compatible = "fixed-clock";
 299 +                               clock-frequency = <40000000>;
 300 +                       };
 301 +               };
 302 +       };
 303 +       fragment@7 {
 304 +               target = <&spi0>;
 305 +               __overlay__ {
 306 +                       status = "okay";
 307 +                       #address-cells = <1>;
 308 +                       #size-cells = <0>;
 309 +                       mcp251xfd@1 {
 310 +                               compatible = "microchip,mcp251xfd";
 311 +                               reg = <1>;
 312 +                               pinctrl-names = "default";
 313 +                               pinctrl-0 = <&mcp251xfd_pins_1>;
 314 +                               spi-max-frequency = <20000000>;
 315 +                               interrupt-parent = <&gpio>;
 316 +                               interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
 317 +                               clocks = <&clk_mcp251xfd_osc_1>;
 318 +                       };
 319 +               };
 320 +       };
 321 +};