plat/amlogic/gxbb/gxbb_def.h

   1 /*
   2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef GXBB_DEF_H
   8 #define GXBB_DEF_H
   9
  10 #include <lib/utils_def.h>
  11
  12 /*******************************************************************************
  13  * System oscillator
  14  ******************************************************************************/
  15 #define AML_OSC24M_CLK_IN_HZ                    ULL(24000000) /* 24 MHz */
  16
  17 /*******************************************************************************
  18  * Memory regions
  19  ******************************************************************************/
  20 #define AML_NSDRAM0_BASE                        UL(0x01000000)
  21 #define AML_NSDRAM0_SIZE                        UL(0x0F000000)
  22
  23 #define AML_NSDRAM1_BASE                        UL(0x10000000)
  24 #define AML_NSDRAM1_SIZE                        UL(0x00100000)
  25
  26 #define BL31_BASE                               UL(0x10100000)
  27 #define BL31_SIZE                               UL(0x000C0000)
  28 #define BL31_LIMIT                              (BL31_BASE + BL31_SIZE)
  29
  30 /* Shared memory used for SMC services */
  31 #define AML_SHARE_MEM_INPUT_BASE                UL(0x100FE000)
  32 #define AML_SHARE_MEM_OUTPUT_BASE               UL(0x100FF000)
  33
  34 #define AML_SEC_DEVICE0_BASE                    UL(0xC0000000)
  35 #define AML_SEC_DEVICE0_SIZE                    UL(0x09000000)
  36
  37 #define AML_SEC_DEVICE1_BASE                    UL(0xD0040000)
  38 #define AML_SEC_DEVICE1_SIZE                    UL(0x00008000)
  39
  40 #define AML_TZRAM_BASE                          UL(0xD9000000)
  41 #define AML_TZRAM_SIZE                          UL(0x00014000)
  42 /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
  43
  44 /* Mailboxes */
  45 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD        UL(0xD9013800)
  46 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD        UL(0xD9013A00)
  47 #define AML_PSCI_MAILBOX_BASE                   UL(0xD9013F00)
  48
  49 #define AML_TZROM_BASE                          UL(0xD9040000)
  50 #define AML_TZROM_SIZE                          UL(0x00010000)
  51
  52 #define AML_SEC_DEVICE2_BASE                    UL(0xDA000000)
  53 #define AML_SEC_DEVICE2_SIZE                    UL(0x00200000)
  54
  55 #define AML_SEC_DEVICE3_BASE                    UL(0xDA800000)
  56 #define AML_SEC_DEVICE3_SIZE                    UL(0x00200000)
  57
  58 /*******************************************************************************
  59  * GIC-400 and interrupt handling related constants
  60  ******************************************************************************/
  61 #define AML_GICD_BASE                           UL(0xC4301000)
  62 #define AML_GICC_BASE                           UL(0xC4302000)
  63
  64 #define IRQ_SEC_PHY_TIMER                       29
  65
  66 #define IRQ_SEC_SGI_0                           8
  67 #define IRQ_SEC_SGI_1                           9
  68 #define IRQ_SEC_SGI_2                           10
  69 #define IRQ_SEC_SGI_3                           11
  70 #define IRQ_SEC_SGI_4                           12
  71 #define IRQ_SEC_SGI_5                           13
  72 #define IRQ_SEC_SGI_6                           14
  73 #define IRQ_SEC_SGI_7                           15
  74
  75 /*******************************************************************************
  76  * UART definitions
  77  ******************************************************************************/
  78 #define AML_UART0_AO_BASE                       UL(0xC81004C0)
  79 #define AML_UART0_AO_CLK_IN_HZ                  AML_OSC24M_CLK_IN_HZ
  80 #define AML_UART_BAUDRATE                       U(115200)
  81
  82 /*******************************************************************************
  83  * Memory-mapped I/O Registers
  84  ******************************************************************************/
  85 #define AML_AO_TIMESTAMP_CNTL                   UL(0xC81000B4)
  86
  87 #define AML_SYS_CPU_CFG7                        UL(0xC8834664)
  88
  89 #define AML_AO_RTI_STATUS_REG3                  UL(0xDA10001C)
  90
  91 #define AML_HIU_MAILBOX_SET_0                   UL(0xDA83C404)
  92 #define AML_HIU_MAILBOX_STAT_0                  UL(0xDA83C408)
  93 #define AML_HIU_MAILBOX_CLR_0                   UL(0xDA83C40C)
  94 #define AML_HIU_MAILBOX_SET_3                   UL(0xDA83C428)
  95 #define AML_HIU_MAILBOX_STAT_3                  UL(0xDA83C42C)
  96 #define AML_HIU_MAILBOX_CLR_3                   UL(0xDA83C430)
  97
  98 #define AML_SHA_DMA_BASE                        UL(0xC883E000)
  99 #define AML_SHA_DMA_DESC                        (AML_SHA_DMA_BASE + 0x08)
 100 #define AML_SHA_DMA_STATUS                      (AML_SHA_DMA_BASE + 0x18)
 101
 102 /*******************************************************************************
 103  * System Monitor Call IDs and arguments
 104  ******************************************************************************/
 105 #define AML_SM_GET_SHARE_MEM_INPUT_BASE         U(0x82000020)
 106 #define AML_SM_GET_SHARE_MEM_OUTPUT_BASE        U(0x82000021)
 107
 108 #define AML_SM_EFUSE_READ                       U(0x82000030)
 109 #define AML_SM_EFUSE_USER_MAX                   U(0x82000033)
 110
 111 #define AML_SM_JTAG_ON                          U(0x82000040)
 112 #define AML_SM_JTAG_OFF                         U(0x82000041)
 113 #define AML_SM_GET_CHIP_ID                      U(0x82000044)
 114
 115 #define AML_JTAG_STATE_ON                       U(0)
 116 #define AML_JTAG_STATE_OFF                      U(1)
 117
 118 #define AML_JTAG_M3_AO                          U(0)
 119 #define AML_JTAG_M3_EE                          U(1)
 120 #define AML_JTAG_A53_AO                         U(2)
 121 #define AML_JTAG_A53_EE                         U(3)
 122
 123 #endif /* GXBB_DEF_H */