package/boot/uboot-mediatek/patches/101-25-net-mediatek-add-support-for-NETSYS-v3.patch

   1 From 7d201749cc49a58fb5e791d1e099ec3e3489e16d Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Wed, 19 Jul 2023 17:17:37 +0800
   4 Subject: [PATCH 25/29] net: mediatek: add support for NETSYS v3
   5
   6 This patch adds support for NETSYS v3 hardware.
   7 Comparing to NETSYS v2, NETSYS v3 has three GMACs.
   8
   9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  10 ---
  11  drivers/net/mtk_eth.c | 49 ++++++++++++++++++++++++++++++++-----------
  12  drivers/net/mtk_eth.h |  7 +++++++
  13  2 files changed, 44 insertions(+), 12 deletions(-)
  14
  15 --- a/drivers/net/mtk_eth.c
  16 +++ b/drivers/net/mtk_eth.c
  17 @@ -76,6 +76,7 @@ enum mtk_switch {
  18   * @caps                       Flags shown the extra capability for the SoC
  19   * @ana_rgc3:                  The offset for register ANA_RGC3 related to
  20   *                             sgmiisys syscon
  21 + * @gdma_count:                        Number of GDMAs
  22   * @pdma_base:                 Register base of PDMA block
  23   * @txd_size:                  Tx DMA descriptor size.
  24   * @rxd_size:                  Rx DMA descriptor size.
  25 @@ -83,6 +84,7 @@ enum mtk_switch {
  26  struct mtk_soc_data {
  27         u32 caps;
  28         u32 ana_rgc3;
  29 +       u32 gdma_count;
  30         u32 pdma_base;
  31         u32 txd_size;
  32         u32 rxd_size;
  33 @@ -159,7 +161,9 @@ static void mtk_gdma_write(struct mtk_et
  34  {
  35         u32 gdma_base;
  36
  37 -       if (no == 1)
  38 +       if (no == 2)
  39 +               gdma_base = GDMA3_BASE;
  40 +       else if (no == 1)
  41                 gdma_base = GDMA2_BASE;
  42         else
  43                 gdma_base = GDMA1_BASE;
  44 @@ -1429,7 +1433,10 @@ static void mtk_eth_fifo_init(struct mtk
  45                 txd->txd1 = virt_to_phys(pkt_base);
  46                 txd->txd2 = PDMA_TXD2_DDONE | PDMA_TXD2_LS0;
  47
  48 -               if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
  49 +               if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
  50 +                       txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id == 2 ?
  51 +                                                          15 : priv->gmac_id + 1);
  52 +               else if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
  53                         txd->txd5 = PDMA_V2_TXD5_FPORT_SET(priv->gmac_id + 1);
  54                 else
  55                         txd->txd4 = PDMA_V1_TXD4_FPORT_SET(priv->gmac_id + 1);
  56 @@ -1442,7 +1449,8 @@ static void mtk_eth_fifo_init(struct mtk
  57
  58                 rxd->rxd1 = virt_to_phys(pkt_base);
  59
  60 -               if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
  61 +               if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
  62 +                   MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
  63                         rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
  64                 else
  65                         rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
  66 @@ -1466,7 +1474,7 @@ static void mtk_eth_fifo_init(struct mtk
  67  static int mtk_eth_start(struct udevice *dev)
  68  {
  69         struct mtk_eth_priv *priv = dev_get_priv(dev);
  70 -       int ret;
  71 +       int i, ret;
  72
  73         /* Reset FE */
  74         reset_assert(&priv->rst_fe);
  75 @@ -1474,16 +1482,24 @@ static int mtk_eth_start(struct udevice
  76         reset_deassert(&priv->rst_fe);
  77         mdelay(10);
  78
  79 -       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
  80 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
  81 +           MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
  82                 setbits_le32(priv->fe_base + FE_GLO_MISC_REG, PDMA_VER_V2);
  83
  84         /* Packets forward to PDMA */
  85         mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU);
  86
  87 -       if (priv->gmac_id == 0)
  88 -               mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
  89 -       else
  90 -               mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
  91 +       for (i = 0; i < priv->soc->gdma_count; i++) {
  92 +               if (i == priv->gmac_id)
  93 +                       continue;
  94 +
  95 +               mtk_gdma_write(priv, i, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD);
  96 +       }
  97 +
  98 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3)) {
  99 +               mtk_gdma_write(priv, priv->gmac_id, GDMA_EG_CTRL_REG,
 100 +                              GDMA_CPU_BRIDGE_EN);
 101 +       }
 102
 103         udelay(500);
 104
 105 @@ -1557,7 +1573,8 @@ static int mtk_eth_send(struct udevice *
 106         flush_dcache_range((ulong)pkt_base, (ulong)pkt_base +
 107                            roundup(length, ARCH_DMA_MINALIGN));
 108
 109 -       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
 110 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
 111 +           MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 112                 txd->txd2 = PDMA_TXD2_LS0 | PDMA_V2_TXD2_SDL0_SET(length);
 113         else
 114                 txd->txd2 = PDMA_TXD2_LS0 | PDMA_V1_TXD2_SDL0_SET(length);
 115 @@ -1583,7 +1600,8 @@ static int mtk_eth_recv(struct udevice *
 116                 return -EAGAIN;
 117         }
 118
 119 -       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
 120 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
 121 +           MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 122                 length = PDMA_V2_RXD2_PLEN0_GET(rxd->rxd2);
 123         else
 124                 length = PDMA_V1_RXD2_PLEN0_GET(rxd->rxd2);
 125 @@ -1606,7 +1624,8 @@ static int mtk_eth_free_pkt(struct udevi
 126
 127         rxd = priv->rx_ring_noc + idx * priv->soc->rxd_size;
 128
 129 -       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2))
 130 +       if (MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V2) ||
 131 +           MTK_HAS_CAPS(priv->soc->caps, MTK_NETSYS_V3))
 132                 rxd->rxd2 = PDMA_V2_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
 133         else
 134                 rxd->rxd2 = PDMA_V1_RXD2_PLEN0_SET(PKTSIZE_ALIGN);
 135 @@ -1863,6 +1882,7 @@ static int mtk_eth_of_to_plat(struct ude
 136  static const struct mtk_soc_data mt7986_data = {
 137         .caps = MT7986_CAPS,
 138         .ana_rgc3 = 0x128,
 139 +       .gdma_count = 2,
 140         .pdma_base = PDMA_V2_BASE,
 141         .txd_size = sizeof(struct mtk_tx_dma_v2),
 142         .rxd_size = sizeof(struct mtk_rx_dma_v2),
 143 @@ -1871,6 +1891,7 @@ static const struct mtk_soc_data mt7986_
 144  static const struct mtk_soc_data mt7981_data = {
 145         .caps = MT7981_CAPS,
 146         .ana_rgc3 = 0x128,
 147 +       .gdma_count = 2,
 148         .pdma_base = PDMA_V2_BASE,
 149         .txd_size = sizeof(struct mtk_tx_dma_v2),
 150         .rxd_size = sizeof(struct mtk_rx_dma_v2),
 151 @@ -1878,6 +1899,7 @@ static const struct mtk_soc_data mt7981_
 152
 153  static const struct mtk_soc_data mt7629_data = {
 154         .ana_rgc3 = 0x128,
 155 +       .gdma_count = 2,
 156         .pdma_base = PDMA_V1_BASE,
 157         .txd_size = sizeof(struct mtk_tx_dma),
 158         .rxd_size = sizeof(struct mtk_rx_dma),
 159 @@ -1885,6 +1907,7 @@ static const struct mtk_soc_data mt7629_
 160
 161  static const struct mtk_soc_data mt7623_data = {
 162         .caps = MT7623_CAPS,
 163 +       .gdma_count = 2,
 164         .pdma_base = PDMA_V1_BASE,
 165         .txd_size = sizeof(struct mtk_tx_dma),
 166         .rxd_size = sizeof(struct mtk_rx_dma),
 167 @@ -1892,6 +1915,7 @@ static const struct mtk_soc_data mt7623_
 168
 169  static const struct mtk_soc_data mt7622_data = {
 170         .ana_rgc3 = 0x2028,
 171 +       .gdma_count = 2,
 172         .pdma_base = PDMA_V1_BASE,
 173         .txd_size = sizeof(struct mtk_tx_dma),
 174         .rxd_size = sizeof(struct mtk_rx_dma),
 175 @@ -1899,6 +1923,7 @@ static const struct mtk_soc_data mt7622_
 176
 177  static const struct mtk_soc_data mt7621_data = {
 178         .caps = MT7621_CAPS,
 179 +       .gdma_count = 2,
 180         .pdma_base = PDMA_V1_BASE,
 181         .txd_size = sizeof(struct mtk_tx_dma),
 182         .rxd_size = sizeof(struct mtk_rx_dma),
 183 --- a/drivers/net/mtk_eth.h
 184 +++ b/drivers/net/mtk_eth.h
 185 @@ -18,6 +18,7 @@ enum mkt_eth_capabilities {
 186         MTK_U3_COPHY_V2_BIT,
 187         MTK_INFRA_BIT,
 188         MTK_NETSYS_V2_BIT,
 189 +       MTK_NETSYS_V3_BIT,
 190
 191         /* PATH BITS */
 192         MTK_ETH_PATH_GMAC1_TRGMII_BIT,
 193 @@ -29,6 +30,7 @@ enum mkt_eth_capabilities {
 194  #define MTK_U3_COPHY_V2                        BIT(MTK_U3_COPHY_V2_BIT)
 195  #define MTK_INFRA                      BIT(MTK_INFRA_BIT)
 196  #define MTK_NETSYS_V2                  BIT(MTK_NETSYS_V2_BIT)
 197 +#define MTK_NETSYS_V3                  BIT(MTK_NETSYS_V3_BIT)
 198
 199  /* Supported path present on SoCs */
 200  #define MTK_ETH_PATH_GMAC1_TRGMII      BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT)
 201 @@ -52,8 +54,10 @@ enum mkt_eth_capabilities {
 202  /* Frame Engine Register Bases */
 203  #define PDMA_V1_BASE                   0x0800
 204  #define PDMA_V2_BASE                   0x6000
 205 +#define PDMA_V3_BASE                   0x6800
 206  #define GDMA1_BASE                     0x0500
 207  #define GDMA2_BASE                     0x1500
 208 +#define GDMA3_BASE                     0x0540
 209  #define GMAC_BASE                      0x10000
 210
 211  /* Ethernet subsystem registers */
 212 @@ -153,6 +157,9 @@ enum mkt_eth_capabilities {
 213  #define UN_DP_S                                0
 214  #define UN_DP_M                                0x0f
 215
 216 +#define GDMA_EG_CTRL_REG               0x004
 217 +#define GDMA_CPU_BRIDGE_EN             BIT(31)
 218 +
 219  #define GDMA_MAC_LSB_REG               0x008
 220
 221  #define GDMA_MAC_MSB_REG               0x00c