bl2u/aarch64/bl2u_entrypoint.S

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <asm_macros.S>
   9 #include <common/bl_common.h>
  10
  11         .globl  bl2u_entrypoint
  12
  13
  14 func bl2u_entrypoint
  15         /*---------------------------------------------
  16          * Store the extents of the tzram available to
  17          * BL2U and other platform specific information
  18          * for future use. x0 is currently not used.
  19          * ---------------------------------------------
  20          */
  21         mov     x20, x1
  22         mov     x21, x2
  23
  24         /* ---------------------------------------------
  25          * Set the exception vector to something sane.
  26          * ---------------------------------------------
  27          */
  28         adr     x0, early_exceptions
  29         msr     vbar_el1, x0
  30         isb
  31
  32         /* ---------------------------------------------
  33          * Enable the SError interrupt now that the
  34          * exception vectors have been setup.
  35          * ---------------------------------------------
  36          */
  37         msr     daifclr, #DAIF_ABT_BIT
  38
  39         /* ---------------------------------------------
  40          * Enable the instruction cache, stack pointer
  41          * and data access alignment checks and disable
  42          * speculative loads.
  43          * ---------------------------------------------
  44          */
  45         mov     x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
  46         mrs     x0, sctlr_el1
  47         orr     x0, x0, x1
  48         bic     x0, x0, #SCTLR_DSSBS_BIT
  49         msr     sctlr_el1, x0
  50         isb
  51
  52         /* ---------------------------------------------
  53          * Invalidate the RW memory used by the BL2U
  54          * image. This includes the data and NOBITS
  55          * sections. This is done to safeguard against
  56          * possible corruption of this memory by dirty
  57          * cache lines in a system cache as a result of
  58          * use by an earlier boot loader stage.
  59          * ---------------------------------------------
  60          */
  61         adr     x0, __RW_START__
  62         adr     x1, __RW_END__
  63         sub     x1, x1, x0
  64         bl      inv_dcache_range
  65
  66         /* ---------------------------------------------
  67          * Zero out NOBITS sections. There are 2 of them:
  68          *   - the .bss section;
  69          *   - the coherent memory section.
  70          * ---------------------------------------------
  71          */
  72         ldr     x0, =__BSS_START__
  73         ldr     x1, =__BSS_SIZE__
  74         bl      zeromem
  75
  76         /* --------------------------------------------
  77          * Allocate a stack whose memory will be marked
  78          * as Normal-IS-WBWA when the MMU is enabled.
  79          * There is no risk of reading stale stack
  80          * memory after enabling the MMU as only the
  81          * primary cpu is running at the moment.
  82          * --------------------------------------------
  83          */
  84         bl      plat_set_my_stack
  85
  86         /* ---------------------------------------------
  87          * Initialize the stack protector canary before
  88          * any C code is called.
  89          * ---------------------------------------------
  90          */
  91 #if STACK_PROTECTOR_ENABLED
  92         bl      update_stack_protector_canary
  93 #endif
  94
  95         /* ---------------------------------------------
  96          * Perform early platform setup & platform
  97          * specific early arch. setup e.g. mmu setup
  98          * ---------------------------------------------
  99          */
 100         mov     x0, x20
 101         mov     x1, x21
 102         bl      bl2u_early_platform_setup
 103         bl      bl2u_plat_arch_setup
 104
 105 #if ENABLE_PAUTH
 106         /* ---------------------------------------------
 107          * Program APIAKey_EL1
 108          * and enable pointer authentication.
 109          * ---------------------------------------------
 110          */
 111         bl      pauth_init_enable_el1
 112 #endif
 113
 114         /* ---------------------------------------------
 115          * Jump to bl2u_main function.
 116          * ---------------------------------------------
 117          */
 118         bl      bl2u_main
 119
 120         /* ---------------------------------------------
 121          * Should never reach this point.
 122          * ---------------------------------------------
 123          */
 124         no_ret  plat_panic_handler
 125
 126 endfunc bl2u_entrypoint