arch/arm/mach-uniphier/debug-uart/debug-uart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
   4  */
   5
   6 #include <common.h>
   7 #include <debug_uart.h>
   8 #include <linux/io.h>
   9 #include <linux/serial_reg.h>
  10
  11 #include "../sg-regs.h"
  12 #include "../soc-info.h"
  13 #include "debug-uart.h"
  14
  15 #define UNIPHIER_UART_TX                0x00
  16 #define UNIPHIER_UART_LCR_MCR           0x10
  17 #define UNIPHIER_UART_LSR               0x14
  18 #define UNIPHIER_UART_LDR               0x24
  19
  20 static void _debug_uart_putc(int c)
  21 {
  22         void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  23
  24         while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
  25                 ;
  26
  27         writel(c, base + UNIPHIER_UART_TX);
  28 }
  29
  30 #ifdef CONFIG_SPL_BUILD
  31 void sg_set_pinsel(unsigned int pin, unsigned int muxval,
  32                    unsigned int mux_bits, unsigned int reg_stride)
  33 {
  34         unsigned int shift = pin * mux_bits % 32;
  35         unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
  36         u32 mask = (1U << mux_bits) - 1;
  37         u32 tmp;
  38
  39         tmp = readl(reg);
  40         tmp &= ~(mask << shift);
  41         tmp |= (mask & muxval) << shift;
  42         writel(tmp, reg);
  43 }
  44
  45 void sg_set_iectrl(unsigned int pin)
  46 {
  47         unsigned int bit = pin % 32;
  48         unsigned long reg = SG_IECTRL + pin / 32 * 4;
  49         u32 tmp;
  50
  51         tmp = readl(reg);
  52         tmp |= 1 << bit;
  53         writel(tmp, reg);
  54 }
  55 #endif
  56
  57 void _debug_uart_init(void)
  58 {
  59 #ifdef CONFIG_SPL_BUILD
  60         void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  61         unsigned int divisor;
  62
  63         switch (uniphier_get_soc_id()) {
  64 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
  65         case UNIPHIER_LD4_ID:
  66                 divisor = uniphier_ld4_debug_uart_init();
  67                 break;
  68 #endif
  69 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
  70         case UNIPHIER_PRO4_ID:
  71                 divisor = uniphier_pro4_debug_uart_init();
  72                 break;
  73 #endif
  74 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
  75         case UNIPHIER_SLD8_ID:
  76                 divisor = uniphier_sld8_debug_uart_init();
  77                 break;
  78 #endif
  79 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
  80         case UNIPHIER_PRO5_ID:
  81                 divisor = uniphier_pro5_debug_uart_init();
  82                 break;
  83 #endif
  84 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
  85         case UNIPHIER_PXS2_ID:
  86                 divisor = uniphier_pxs2_debug_uart_init();
  87                 break;
  88 #endif
  89 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
  90         case UNIPHIER_LD6B_ID:
  91                 divisor = uniphier_ld6b_debug_uart_init();
  92                 break;
  93 #endif
  94         default:
  95                 return;
  96         }
  97
  98         writel(UART_LCR_WLEN8 << 8, base + UNIPHIER_UART_LCR_MCR);
  99
 100         writel(divisor, base + UNIPHIER_UART_LDR);
 101 #endif
 102 }
 103 DEBUG_UART_FUNCS