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realtek: 5.15: rtl93xx: support 2500baseT and 5000baseT on USXGMII links
[openwrt/openwrt.git] / target / linux / realtek / files-5.15 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/etherdevice.h>
5 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7
8 #include "rtl83xx.h"
9
10 extern struct rtl83xx_soc_info soc_info;
11
12 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
13 {
14 mutex_lock(&priv->reg_mutex);
15
16 /* Enable statistics module: all counters plus debug.
17 * On RTL839x all counters are enabled by default
18 */
19 if (priv->family_id == RTL8380_FAMILY_ID)
20 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
21
22 /* Reset statistics counters */
23 sw_w32_mask(0, 1, priv->r->stat_rst);
24
25 mutex_unlock(&priv->reg_mutex);
26 }
27
28 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
29 {
30 u64 v = 0;
31
32 msleep(1000);
33 /* Enable all ports with a PHY, including the SFP-ports */
34 for (int i = 0; i < priv->cpu_port; i++) {
35 if (priv->ports[i].phy)
36 v |= BIT_ULL(i);
37 }
38
39 pr_info("%s: %16llx\n", __func__, v);
40 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
41
42 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
43 if (priv->family_id == RTL8390_FAMILY_ID)
44 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
45 else if(priv->family_id == RTL9300_FAMILY_ID)
46 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
47 }
48
49 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
50 MIB_DESC(2, 0xf8, "ifInOctets"),
51 MIB_DESC(2, 0xf0, "ifOutOctets"),
52 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
53 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
54 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
55 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
56 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
57 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
58 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
59 MIB_DESC(1, 0xd0, "ifOutDiscards"),
60 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
61 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
62 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
63 MIB_DESC(1, 0xc0, ".3LateCollisions"),
64 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
65 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
66 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
67 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
68 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
69 MIB_DESC(1, 0xa8, "DropEvents"),
70 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
71 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
72 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
73 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
74 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
75 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
76 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
77 MIB_DESC(1, 0x88, "rx_OversizePkts"),
78 MIB_DESC(1, 0x84, "Fragments"),
79 MIB_DESC(1, 0x80, "Jabbers"),
80 MIB_DESC(1, 0x7c, "Collisions"),
81 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
82 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
83 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
84 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
85 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
86 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
87 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
88 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
89 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
90 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
91 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
92 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
93 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
94 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
95 MIB_DESC(1, 0x40, "rxMacDiscards")
96 };
97
98
99 /* DSA callbacks */
100
101
102 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
103 int port,
104 enum dsa_tag_protocol mprot)
105 {
106 /* The switch does not tag the frames, instead internally the header
107 * structure for each packet is tagged accordingly.
108 */
109 return DSA_TAG_PROTO_TRAILER;
110 }
111
112 /* Initialize all VLANS */
113 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
114 {
115 struct rtl838x_vlan_info info;
116
117 pr_info("In %s\n", __func__);
118
119 priv->r->vlan_profile_setup(0);
120 priv->r->vlan_profile_setup(1);
121 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
122 priv->r->vlan_profile_dump(0);
123
124 info.fid = 0; /* Default Forwarding ID / MSTI */
125 info.hash_uc_fid = false; /* Do not build the L2 lookup hash with FID, but VID */
126 info.hash_mc_fid = false; /* Do the same for Multicast packets */
127 info.profile_id = 0; /* Use default Vlan Profile 0 */
128 info.tagged_ports = 0; /* Initially no port members */
129 if (priv->family_id == RTL9310_FAMILY_ID) {
130 info.if_id = 0;
131 info.multicast_grp_mask = 0;
132 info.l2_tunnel_list_id = -1;
133 }
134
135 /* Initialize all vlans 0-4095 */
136 for (int i = 0; i < MAX_VLANS; i ++)
137 priv->r->vlan_set_tagged(i, &info);
138
139 /* reset PVIDs; defaults to 1 on reset */
140 for (int i = 0; i <= priv->ds->num_ports; i++) {
141 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_INNER, 0);
142 priv->r->vlan_port_pvid_set(i, PBVLAN_TYPE_OUTER, 0);
143 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_INNER, PBVLAN_MODE_UNTAG_AND_PRITAG);
144 priv->r->vlan_port_pvidmode_set(i, PBVLAN_TYPE_OUTER, PBVLAN_MODE_UNTAG_AND_PRITAG);
145 }
146
147 /* Set forwarding action based on inner VLAN tag */
148 for (int i = 0; i < priv->cpu_port; i++)
149 priv->r->vlan_fwd_on_inner(i, true);
150 }
151
152 static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv)
153 {
154 for (int i = 0; i < priv->cpu_port; i++)
155 priv->r->set_receive_management_action(i, BPDU, COPY2CPU);
156 }
157
158 static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv,
159 int port, bool enable)
160 {
161 int shift = SALRN_PORT_SHIFT(port);
162 int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED;
163
164 sw_w32_mask(SALRN_MODE_MASK << shift, val << shift,
165 priv->r->l2_port_new_salrn(port));
166 }
167
168 static int rtl83xx_setup(struct dsa_switch *ds)
169 {
170 struct rtl838x_switch_priv *priv = ds->priv;
171
172 pr_debug("%s called\n", __func__);
173
174 /* Disable MAC polling the PHY so that we can start configuration */
175 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
176
177 for (int i = 0; i < ds->num_ports; i++)
178 priv->ports[i].enable = false;
179 priv->ports[priv->cpu_port].enable = true;
180
181 /* Configure ports so they are disabled by default, but once enabled
182 * they will work in isolated mode (only traffic between port and CPU).
183 */
184 for (int i = 0; i < priv->cpu_port; i++) {
185 if (priv->ports[i].phy) {
186 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
187 priv->r->traffic_set(i, BIT_ULL(i));
188 }
189 }
190 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
191
192 /* For standalone ports, forward packets even if a static fdb
193 * entry for the source address exists on another port.
194 */
195 if (priv->r->set_static_move_action) {
196 for (int i = 0; i <= priv->cpu_port; i++)
197 priv->r->set_static_move_action(i, true);
198 }
199
200 if (priv->family_id == RTL8380_FAMILY_ID)
201 rtl838x_print_matrix();
202 else
203 rtl839x_print_matrix();
204
205 rtl83xx_init_stats(priv);
206
207 rtl83xx_vlan_setup(priv);
208
209 rtl83xx_setup_bpdu_traps(priv);
210
211 ds->configure_vlan_while_not_filtering = true;
212
213 priv->r->l2_learning_setup();
214
215 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
216 ds->assisted_learning_on_cpu_port = true;
217
218 /* Make sure all frames sent to the switch's MAC are trapped to the CPU-port
219 * 0: FWD, 1: DROP, 2: TRAP2CPU
220 */
221 if (priv->family_id == RTL8380_FAMILY_ID)
222 sw_w32(0x2, RTL838X_SPCL_TRAP_SWITCH_MAC_CTRL);
223 else
224 sw_w32(0x2, RTL839X_SPCL_TRAP_SWITCH_MAC_CTRL);
225
226 /* Enable MAC Polling PHY again */
227 rtl83xx_enable_phy_polling(priv);
228 pr_debug("Please wait until PHY is settled\n");
229 msleep(1000);
230 priv->r->pie_init(priv);
231
232 return 0;
233 }
234
235 static int rtl93xx_setup(struct dsa_switch *ds)
236 {
237 struct rtl838x_switch_priv *priv = ds->priv;
238
239 pr_info("%s called\n", __func__);
240
241 /* Disable MAC polling the PHY so that we can start configuration */
242 if (priv->family_id == RTL9300_FAMILY_ID)
243 sw_w32(0, RTL930X_SMI_POLL_CTRL);
244
245 if (priv->family_id == RTL9310_FAMILY_ID) {
246 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
247 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
248 }
249
250 /* Disable all ports except CPU port */
251 for (int i = 0; i < ds->num_ports; i++)
252 priv->ports[i].enable = false;
253 priv->ports[priv->cpu_port].enable = true;
254
255 /* Configure ports so they are disabled by default, but once enabled
256 * they will work in isolated mode (only traffic between port and CPU).
257 */
258 for (int i = 0; i < priv->cpu_port; i++) {
259 if (priv->ports[i].phy) {
260 priv->ports[i].pm = BIT_ULL(priv->cpu_port);
261 priv->r->traffic_set(i, BIT_ULL(i));
262 }
263 }
264 priv->r->traffic_set(priv->cpu_port, BIT_ULL(priv->cpu_port));
265
266 rtl930x_print_matrix();
267
268 /* TODO: Initialize statistics */
269
270 rtl83xx_vlan_setup(priv);
271
272 ds->configure_vlan_while_not_filtering = true;
273
274 priv->r->l2_learning_setup();
275
276 rtl83xx_port_set_salrn(priv, priv->cpu_port, false);
277 ds->assisted_learning_on_cpu_port = true;
278
279 rtl83xx_enable_phy_polling(priv);
280
281 priv->r->pie_init(priv);
282
283 priv->r->led_init(priv);
284
285 return 0;
286 }
287
288 static int rtl93xx_get_sds(struct phy_device *phydev)
289 {
290 struct device *dev = &phydev->mdio.dev;
291 struct device_node *dn;
292 u32 sds_num;
293
294 if (!dev)
295 return -1;
296 if (dev->of_node) {
297 dn = dev->of_node;
298 if (of_property_read_u32(dn, "sds", &sds_num))
299 sds_num = -1;
300 } else {
301 dev_err(dev, "No DT node.\n");
302 return -1;
303 }
304
305 return sds_num;
306 }
307
308 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
309 unsigned long *supported,
310 struct phylink_link_state *state)
311 {
312 struct rtl838x_switch_priv *priv = ds->priv;
313 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
314
315 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
316
317 if (!phy_interface_mode_is_rgmii(state->interface) &&
318 state->interface != PHY_INTERFACE_MODE_NA &&
319 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
320 state->interface != PHY_INTERFACE_MODE_MII &&
321 state->interface != PHY_INTERFACE_MODE_REVMII &&
322 state->interface != PHY_INTERFACE_MODE_GMII &&
323 state->interface != PHY_INTERFACE_MODE_QSGMII &&
324 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
325 state->interface != PHY_INTERFACE_MODE_SGMII) {
326 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
327 dev_err(ds->dev,
328 "Unsupported interface: %d for port %d\n",
329 state->interface, port);
330 return;
331 }
332
333 /* Allow all the expected bits */
334 phylink_set(mask, Autoneg);
335 phylink_set_port_modes(mask);
336 phylink_set(mask, Pause);
337 phylink_set(mask, Asym_Pause);
338
339 /* With the exclusion of MII and Reverse MII, we support Gigabit,
340 * including Half duplex
341 */
342 if (state->interface != PHY_INTERFACE_MODE_MII &&
343 state->interface != PHY_INTERFACE_MODE_REVMII) {
344 phylink_set(mask, 1000baseT_Full);
345 phylink_set(mask, 1000baseT_Half);
346 }
347
348 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
349 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
350 phylink_set(mask, 1000baseX_Full);
351
352 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
353 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
354 phylink_set(mask, 1000baseX_Full);
355
356 phylink_set(mask, 10baseT_Half);
357 phylink_set(mask, 10baseT_Full);
358 phylink_set(mask, 100baseT_Half);
359 phylink_set(mask, 100baseT_Full);
360
361 bitmap_and(supported, supported, mask,
362 __ETHTOOL_LINK_MODE_MASK_NBITS);
363 bitmap_and(state->advertising, state->advertising, mask,
364 __ETHTOOL_LINK_MODE_MASK_NBITS);
365 }
366
367 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
368 unsigned long *supported,
369 struct phylink_link_state *state)
370 {
371 struct rtl838x_switch_priv *priv = ds->priv;
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
375 phy_modes(state->interface));
376
377 if (!phy_interface_mode_is_rgmii(state->interface) &&
378 state->interface != PHY_INTERFACE_MODE_NA &&
379 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
380 state->interface != PHY_INTERFACE_MODE_MII &&
381 state->interface != PHY_INTERFACE_MODE_REVMII &&
382 state->interface != PHY_INTERFACE_MODE_GMII &&
383 state->interface != PHY_INTERFACE_MODE_QSGMII &&
384 state->interface != PHY_INTERFACE_MODE_XGMII &&
385 state->interface != PHY_INTERFACE_MODE_HSGMII &&
386 state->interface != PHY_INTERFACE_MODE_10GBASER &&
387 state->interface != PHY_INTERFACE_MODE_10GKR &&
388 state->interface != PHY_INTERFACE_MODE_USXGMII &&
389 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
390 state->interface != PHY_INTERFACE_MODE_SGMII) {
391 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
392 dev_err(ds->dev,
393 "Unsupported interface: %d for port %d\n",
394 state->interface, port);
395 return;
396 }
397
398 /* Allow all the expected bits */
399 phylink_set(mask, Autoneg);
400 phylink_set_port_modes(mask);
401 phylink_set(mask, Pause);
402 phylink_set(mask, Asym_Pause);
403
404 /* With the exclusion of MII and Reverse MII, we support Gigabit,
405 * including Half duplex
406 */
407 if (state->interface != PHY_INTERFACE_MODE_MII &&
408 state->interface != PHY_INTERFACE_MODE_REVMII) {
409 phylink_set(mask, 1000baseT_Full);
410 phylink_set(mask, 1000baseT_Half);
411 }
412
413 /* Internal phys of the RTL93xx family provide 10G */
414 if (priv->ports[port].phy_is_integrated &&
415 state->interface == PHY_INTERFACE_MODE_1000BASEX) {
416 phylink_set(mask, 1000baseX_Full);
417 } else if (priv->ports[port].phy_is_integrated) {
418 phylink_set(mask, 1000baseX_Full);
419 phylink_set(mask, 10000baseKR_Full);
420 phylink_set(mask, 10000baseSR_Full);
421 phylink_set(mask, 10000baseCR_Full);
422 }
423 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
424 phylink_set(mask, 1000baseX_Full);
425 phylink_set(mask, 1000baseT_Full);
426 phylink_set(mask, 10000baseKR_Full);
427 phylink_set(mask, 10000baseT_Full);
428 phylink_set(mask, 10000baseSR_Full);
429 phylink_set(mask, 10000baseCR_Full);
430 }
431
432 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
433 phylink_set(mask, 2500baseT_Full);
434 phylink_set(mask, 5000baseT_Full);
435 phylink_set(mask, 10000baseT_Full);
436 }
437
438 phylink_set(mask, 10baseT_Half);
439 phylink_set(mask, 10baseT_Full);
440 phylink_set(mask, 100baseT_Half);
441 phylink_set(mask, 100baseT_Full);
442
443 bitmap_and(supported, supported, mask,
444 __ETHTOOL_LINK_MODE_MASK_NBITS);
445 bitmap_and(state->advertising, state->advertising, mask,
446 __ETHTOOL_LINK_MODE_MASK_NBITS);
447 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
448 }
449
450 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
451 struct phylink_link_state *state)
452 {
453 struct rtl838x_switch_priv *priv = ds->priv;
454 u64 speed;
455 u64 link;
456
457 if (port < 0 || port > priv->cpu_port)
458 return -EINVAL;
459
460 state->link = 0;
461 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
462 if (link & BIT_ULL(port))
463 state->link = 1;
464 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
465
466 state->duplex = 0;
467 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
468 state->duplex = 1;
469
470 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
471 speed >>= (port % 16) << 1;
472 switch (speed & 0x3) {
473 case 0:
474 state->speed = SPEED_10;
475 break;
476 case 1:
477 state->speed = SPEED_100;
478 break;
479 case 2:
480 state->speed = SPEED_1000;
481 break;
482 case 3:
483 if (priv->family_id == RTL9300_FAMILY_ID
484 && (port == 24 || port == 26)) /* Internal serdes */
485 state->speed = SPEED_2500;
486 else
487 state->speed = SPEED_100; /* Is in fact 500Mbit */
488 }
489
490 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
491 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
492 state->pause |= MLO_PAUSE_RX;
493 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
494 state->pause |= MLO_PAUSE_TX;
495
496 return 1;
497 }
498
499 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
500 struct phylink_link_state *state)
501 {
502 struct rtl838x_switch_priv *priv = ds->priv;
503 u64 speed;
504 u64 link;
505 u64 media;
506
507 if (port < 0 || port > priv->cpu_port)
508 return -EINVAL;
509
510 /* On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
511 * state needs to be read twice in order to read a correct result.
512 * This would not be necessary for ports connected e.g. to RTL8218D
513 * PHYs.
514 */
515 state->link = 0;
516 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
517 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
518 if (link & BIT_ULL(port))
519 state->link = 1;
520
521 if (priv->family_id == RTL9310_FAMILY_ID)
522 media = priv->r->get_port_reg_le(RTL931X_MAC_LINK_MEDIA_STS);
523
524 if (priv->family_id == RTL9300_FAMILY_ID)
525 media = sw_r32(RTL930X_MAC_LINK_MEDIA_STS);
526
527 if (media & BIT_ULL(port))
528 state->link = 1;
529
530 pr_debug("%s: link state port %d: %llx, media %llx\n", __func__, port,
531 link & BIT_ULL(port), media);
532
533 state->duplex = 0;
534 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
535 state->duplex = 1;
536
537 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
538 speed >>= (port % 8) << 2;
539 switch (speed & 0xf) {
540 case 0:
541 state->speed = SPEED_10;
542 break;
543 case 1:
544 state->speed = SPEED_100;
545 break;
546 case 2:
547 case 7:
548 state->speed = SPEED_1000;
549 break;
550 case 4:
551 state->speed = SPEED_10000;
552 break;
553 case 5:
554 case 8:
555 state->speed = SPEED_2500;
556 break;
557 case 6:
558 state->speed = SPEED_5000;
559 break;
560 default:
561 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
562 }
563
564 if (priv->family_id == RTL9310_FAMILY_ID
565 && (port >= 52 && port <= 55)) { /* Internal serdes */
566 state->speed = SPEED_10000;
567 state->link = 1;
568 state->duplex = 1;
569 }
570
571 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
572 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
573 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
574 state->pause |= MLO_PAUSE_RX;
575 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
576 state->pause |= MLO_PAUSE_TX;
577
578 return 1;
579 }
580
581 static void rtl83xx_config_interface(int port, phy_interface_t interface)
582 {
583 u32 old, int_shift, sds_shift;
584
585 switch (port) {
586 case 24:
587 int_shift = 0;
588 sds_shift = 5;
589 break;
590 case 26:
591 int_shift = 3;
592 sds_shift = 0;
593 break;
594 default:
595 return;
596 }
597
598 old = sw_r32(RTL838X_SDS_MODE_SEL);
599 switch (interface) {
600 case PHY_INTERFACE_MODE_1000BASEX:
601 if ((old >> sds_shift & 0x1f) == 4)
602 return;
603 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
604 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
605 break;
606 case PHY_INTERFACE_MODE_SGMII:
607 if ((old >> sds_shift & 0x1f) == 2)
608 return;
609 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
610 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
611 break;
612 default:
613 return;
614 }
615 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
616 }
617
618 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
619 unsigned int mode,
620 const struct phylink_link_state *state)
621 {
622 struct rtl838x_switch_priv *priv = ds->priv;
623 u32 reg;
624 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
625
626 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
627
628 if (port == priv->cpu_port) {
629 /* Set Speed, duplex, flow control
630 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
631 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
632 * | MEDIA_SEL
633 */
634 if (priv->family_id == RTL8380_FAMILY_ID) {
635 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
636 /* allow CRC errors on CPU-port */
637 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
638 } else {
639 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
640 }
641 return;
642 }
643
644 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
645 /* Auto-Negotiation does not work for MAC in RTL8390 */
646 if (priv->family_id == RTL8380_FAMILY_ID) {
647 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
648 pr_debug("PHY autonegotiates\n");
649 reg |= RTL838X_NWAY_EN;
650 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
651 rtl83xx_config_interface(port, state->interface);
652 return;
653 }
654 }
655
656 if (mode != MLO_AN_FIXED)
657 pr_debug("Fixed state.\n");
658
659 /* Clear id_mode_dis bit, and the existing port mode, let
660 * RGMII_MODE_EN bet set by mac_link_{up,down} */
661 if (priv->family_id == RTL8380_FAMILY_ID) {
662 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
663 if (state->pause & MLO_PAUSE_TXRX_MASK) {
664 if (state->pause & MLO_PAUSE_TX)
665 reg |= RTL838X_TX_PAUSE_EN;
666 reg |= RTL838X_RX_PAUSE_EN;
667 }
668 } else if (priv->family_id == RTL8390_FAMILY_ID) {
669 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
670 if (state->pause & MLO_PAUSE_TXRX_MASK) {
671 if (state->pause & MLO_PAUSE_TX)
672 reg |= RTL839X_TX_PAUSE_EN;
673 reg |= RTL839X_RX_PAUSE_EN;
674 }
675 }
676
677
678 reg &= ~(3 << speed_bit);
679 switch (state->speed) {
680 case SPEED_1000:
681 reg |= 2 << speed_bit;
682 break;
683 case SPEED_100:
684 reg |= 1 << speed_bit;
685 break;
686 default:
687 break; /* Ignore, including 10MBit which has a speed value of 0 */
688 }
689
690 if (priv->family_id == RTL8380_FAMILY_ID) {
691 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
692 if (state->link)
693 reg |= RTL838X_FORCE_LINK_EN;
694 if (state->duplex == RTL838X_DUPLEX_MODE)
695 reg |= RTL838X_DUPLEX_MODE;
696 } else if (priv->family_id == RTL8390_FAMILY_ID) {
697 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
698 if (state->link)
699 reg |= RTL839X_FORCE_LINK_EN;
700 if (state->duplex == RTL839X_DUPLEX_MODE)
701 reg |= RTL839X_DUPLEX_MODE;
702 }
703
704 /* LAG members must use DUPLEX and we need to enable the link */
705 if (priv->lagmembers & BIT_ULL(port)) {
706 switch(priv->family_id) {
707 case RTL8380_FAMILY_ID:
708 reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
709 break;
710 case RTL8390_FAMILY_ID:
711 reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
712 break;
713 }
714 }
715
716 /* Disable AN */
717 if (priv->family_id == RTL8380_FAMILY_ID)
718 reg &= ~RTL838X_NWAY_EN;
719 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
720 }
721
722 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
723 unsigned int mode,
724 const struct phylink_link_state *state)
725 {
726 struct rtl838x_switch_priv *priv = ds->priv;
727 int sds_num;
728 u32 reg, band;
729
730 sds_num = priv->ports[port].sds_num;
731 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
732
733 switch (state->interface) {
734 case PHY_INTERFACE_MODE_HSGMII:
735 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
736 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
737 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
738 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
739 break;
740 case PHY_INTERFACE_MODE_1000BASEX:
741 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
742 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
743 break;
744 case PHY_INTERFACE_MODE_XGMII:
745 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
746 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
747 break;
748 case PHY_INTERFACE_MODE_10GBASER:
749 case PHY_INTERFACE_MODE_10GKR:
750 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
751 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
752 break;
753 case PHY_INTERFACE_MODE_USXGMII:
754 /* Translates to MII_USXGMII_10GSXGMII */
755 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
756 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
757 break;
758 case PHY_INTERFACE_MODE_SGMII:
759 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
760 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
761 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
762 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
763 break;
764 case PHY_INTERFACE_MODE_QSGMII:
765 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
766 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
767 break;
768 default:
769 pr_err("%s: unknown serdes mode: %s\n",
770 __func__, phy_modes(state->interface));
771 return;
772 }
773
774 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
775 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
776
777 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
778
779 reg &= ~(0xf << 12);
780 reg |= 0x2 << 12; /* Set SMI speed to 0x2 */
781
782 reg |= RTL931X_TX_PAUSE_EN | RTL931X_RX_PAUSE_EN;
783
784 if (priv->lagmembers & BIT_ULL(port))
785 reg |= RTL931X_DUPLEX_MODE;
786
787 if (state->duplex == DUPLEX_FULL)
788 reg |= RTL931X_DUPLEX_MODE;
789
790 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
791
792 }
793
794 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
795 unsigned int mode,
796 const struct phylink_link_state *state)
797 {
798 struct rtl838x_switch_priv *priv = ds->priv;
799 int sds_num, sds_mode;
800 u32 reg;
801
802 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
803 port, mode, phy_modes(state->interface), state->speed, state->link);
804
805 /* Nothing to be done for the CPU-port */
806 if (port == priv->cpu_port)
807 return;
808
809 if (priv->family_id == RTL9310_FAMILY_ID)
810 return rtl931x_phylink_mac_config(ds, port, mode, state);
811
812 sds_num = priv->ports[port].sds_num;
813 pr_info("%s SDS is %d\n", __func__, sds_num);
814 if (sds_num >= 0) {
815 switch (state->interface) {
816 case PHY_INTERFACE_MODE_HSGMII:
817 sds_mode = 0x12;
818 break;
819 case PHY_INTERFACE_MODE_1000BASEX:
820 sds_mode = 0x04;
821 break;
822 case PHY_INTERFACE_MODE_XGMII:
823 sds_mode = 0x10;
824 break;
825 case PHY_INTERFACE_MODE_10GBASER:
826 case PHY_INTERFACE_MODE_10GKR:
827 sds_mode = 0x1b; /* 10G 1000X Auto */
828 break;
829 case PHY_INTERFACE_MODE_USXGMII:
830 sds_mode = 0x0d;
831 break;
832 default:
833 pr_err("%s: unknown serdes mode: %s\n",
834 __func__, phy_modes(state->interface));
835 return;
836 }
837 if (state->interface == PHY_INTERFACE_MODE_10GBASER)
838 rtl9300_serdes_setup(sds_num, state->interface);
839 }
840
841 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
842 reg &= ~(0xf << 3);
843
844 switch (state->speed) {
845 case SPEED_10000:
846 reg |= 4 << 3;
847 break;
848 case SPEED_5000:
849 reg |= 6 << 3;
850 break;
851 case SPEED_2500:
852 reg |= 5 << 3;
853 break;
854 case SPEED_1000:
855 reg |= 2 << 3;
856 break;
857 default:
858 reg |= 2 << 3;
859 break;
860 }
861
862 if (state->link)
863 reg |= RTL930X_FORCE_LINK_EN;
864
865 if (priv->lagmembers & BIT_ULL(port))
866 reg |= RTL930X_DUPLEX_MODE | RTL930X_FORCE_LINK_EN;
867
868 if (state->duplex == DUPLEX_FULL)
869 reg |= RTL930X_DUPLEX_MODE;
870
871 if (priv->ports[port].phy_is_integrated)
872 reg &= ~RTL930X_FORCE_EN; /* Clear MAC_FORCE_EN to allow SDS-MAC link */
873 else
874 reg |= RTL930X_FORCE_EN;
875
876 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
877 }
878
879 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
880 unsigned int mode,
881 phy_interface_t interface)
882 {
883 struct rtl838x_switch_priv *priv = ds->priv;
884
885 /* Stop TX/RX to port */
886 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
887
888 /* No longer force link */
889 sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
890 }
891
892 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
893 unsigned int mode,
894 phy_interface_t interface)
895 {
896 struct rtl838x_switch_priv *priv = ds->priv;
897 u32 v = 0;
898
899 /* Stop TX/RX to port */
900 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
901
902 /* No longer force link */
903 if (priv->family_id == RTL9300_FAMILY_ID)
904 v = RTL930X_FORCE_EN | RTL930X_FORCE_LINK_EN;
905 else if (priv->family_id == RTL9310_FAMILY_ID)
906 v = RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN;
907 sw_w32_mask(v, 0, priv->r->mac_force_mode_ctrl(port));
908 }
909
910 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
911 unsigned int mode,
912 phy_interface_t interface,
913 struct phy_device *phydev,
914 int speed, int duplex,
915 bool tx_pause, bool rx_pause)
916 {
917 struct rtl838x_switch_priv *priv = ds->priv;
918 /* Restart TX/RX to port */
919 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
920 /* TODO: Set speed/duplex/pauses */
921 }
922
923 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
924 unsigned int mode,
925 phy_interface_t interface,
926 struct phy_device *phydev,
927 int speed, int duplex,
928 bool tx_pause, bool rx_pause)
929 {
930 struct rtl838x_switch_priv *priv = ds->priv;
931
932 /* Restart TX/RX to port */
933 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
934 /* TODO: Set speed/duplex/pauses */
935 }
936
937 static void rtl83xx_get_strings(struct dsa_switch *ds,
938 int port, u32 stringset, u8 *data)
939 {
940 if (stringset != ETH_SS_STATS)
941 return;
942
943 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
944 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
945 ETH_GSTRING_LEN);
946 }
947
948 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
949 uint64_t *data)
950 {
951 struct rtl838x_switch_priv *priv = ds->priv;
952 const struct rtl83xx_mib_desc *mib;
953 u64 h;
954
955 for (int i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
956 mib = &rtl83xx_mib[i];
957
958 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
959 if (mib->size == 2) {
960 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
961 data[i] |= h << 32;
962 }
963 }
964 }
965
966 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
967 {
968 if (sset != ETH_SS_STATS)
969 return 0;
970
971 return ARRAY_SIZE(rtl83xx_mib);
972 }
973
974 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
975 {
976 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
977 u64 portmask;
978
979 if (mc_group >= MAX_MC_GROUPS - 1)
980 return -1;
981
982 set_bit(mc_group, priv->mc_group_bm);
983 portmask = BIT_ULL(port);
984 priv->r->write_mcast_pmask(mc_group, portmask);
985
986 return mc_group;
987 }
988
989 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
990 {
991 u64 portmask = priv->r->read_mcast_pmask(mc_group);
992
993 pr_debug("%s: %d\n", __func__, port);
994
995 portmask |= BIT_ULL(port);
996 priv->r->write_mcast_pmask(mc_group, portmask);
997
998 return portmask;
999 }
1000
1001 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1002 {
1003 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1004
1005 pr_debug("%s: %d\n", __func__, port);
1006
1007 portmask &= ~BIT_ULL(port);
1008 priv->r->write_mcast_pmask(mc_group, portmask);
1009 if (!portmask)
1010 clear_bit(mc_group, priv->mc_group_bm);
1011
1012 return portmask;
1013 }
1014
1015 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
1016 struct phy_device *phydev)
1017 {
1018 struct rtl838x_switch_priv *priv = ds->priv;
1019 u64 v;
1020
1021 pr_debug("%s: %x %d", __func__, (u32) priv, port);
1022 priv->ports[port].enable = true;
1023
1024 /* enable inner tagging on egress, do not keep any tags */
1025 priv->r->vlan_port_keep_tag_set(port, 0, 1);
1026
1027 if (dsa_is_cpu_port(ds, port))
1028 return 0;
1029
1030 /* add port to switch mask of CPU_PORT */
1031 priv->r->traffic_enable(priv->cpu_port, port);
1032
1033 if (priv->is_lagmember[port]) {
1034 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1035 return 0;
1036 }
1037
1038 /* add all other ports in the same bridge to switch mask of port */
1039 v = priv->r->traffic_get(port);
1040 v |= priv->ports[port].pm;
1041 priv->r->traffic_set(port, v);
1042
1043 /* TODO: Figure out if this is necessary */
1044 if (priv->family_id == RTL9300_FAMILY_ID) {
1045 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
1046 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
1047 }
1048
1049 if (priv->ports[port].sds_num < 0)
1050 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
1051
1052 return 0;
1053 }
1054
1055 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
1056 {
1057 struct rtl838x_switch_priv *priv = ds->priv;
1058 u64 v;
1059
1060 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1061 /* you can only disable user ports */
1062 if (!dsa_is_user_port(ds, port))
1063 return;
1064
1065 /* BUG: This does not work on RTL931X */
1066 /* remove port from switch mask of CPU_PORT */
1067 priv->r->traffic_disable(priv->cpu_port, port);
1068
1069 /* remove all other ports in the same bridge from switch mask of port */
1070 v = priv->r->traffic_get(port);
1071 v &= ~priv->ports[port].pm;
1072 priv->r->traffic_set(port, v);
1073
1074 priv->ports[port].enable = false;
1075 }
1076
1077 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
1078 struct ethtool_eee *e)
1079 {
1080 struct rtl838x_switch_priv *priv = ds->priv;
1081
1082 if (e->eee_enabled && !priv->eee_enabled) {
1083 pr_info("Globally enabling EEE\n");
1084 priv->r->init_eee(priv, true);
1085 }
1086
1087 priv->r->port_eee_set(priv, port, e->eee_enabled);
1088
1089 if (e->eee_enabled)
1090 pr_info("Enabled EEE for port %d\n", port);
1091 else
1092 pr_info("Disabled EEE for port %d\n", port);
1093
1094 return 0;
1095 }
1096
1097 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
1098 struct ethtool_eee *e)
1099 {
1100 struct rtl838x_switch_priv *priv = ds->priv;
1101
1102 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1103
1104 priv->r->eee_port_ability(priv, e, port);
1105
1106 e->eee_enabled = priv->ports[port].eee_enabled;
1107
1108 e->eee_active = !!(e->advertised & e->lp_advertised);
1109
1110 return 0;
1111 }
1112
1113 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
1114 struct ethtool_eee *e)
1115 {
1116 struct rtl838x_switch_priv *priv = ds->priv;
1117
1118 e->supported = SUPPORTED_100baseT_Full |
1119 SUPPORTED_1000baseT_Full |
1120 SUPPORTED_2500baseX_Full;
1121
1122 priv->r->eee_port_ability(priv, e, port);
1123
1124 e->eee_enabled = priv->ports[port].eee_enabled;
1125
1126 e->eee_active = !!(e->advertised & e->lp_advertised);
1127
1128 return 0;
1129 }
1130
1131 static int rtl83xx_set_ageing_time(struct dsa_switch *ds, unsigned int msec)
1132 {
1133 struct rtl838x_switch_priv *priv = ds->priv;
1134
1135 priv->r->set_ageing_time(msec);
1136
1137 return 0;
1138 }
1139
1140 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1141 struct net_device *bridge)
1142 {
1143 struct rtl838x_switch_priv *priv = ds->priv;
1144 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1145
1146 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1147
1148 if (priv->is_lagmember[port]) {
1149 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1150 return 0;
1151 }
1152
1153 mutex_lock(&priv->reg_mutex);
1154 for (int i = 0; i < ds->num_ports; i++) {
1155 /* Add this port to the port matrix of the other ports in the
1156 * same bridge. If the port is disabled, port matrix is kept
1157 * and not being setup until the port becomes enabled.
1158 */
1159 if (dsa_is_user_port(ds, i) && !priv->is_lagmember[i] && i != port) {
1160 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1161 continue;
1162 if (priv->ports[i].enable)
1163 priv->r->traffic_enable(i, port);
1164
1165 priv->ports[i].pm |= BIT_ULL(port);
1166 port_bitmap |= BIT_ULL(i);
1167 }
1168 }
1169
1170 /* Add all other ports to this port matrix. */
1171 if (priv->ports[port].enable) {
1172 priv->r->traffic_enable(priv->cpu_port, port);
1173 v = priv->r->traffic_get(port);
1174 v |= port_bitmap;
1175 priv->r->traffic_set(port, v);
1176 }
1177 priv->ports[port].pm |= port_bitmap;
1178
1179 if (priv->r->set_static_move_action)
1180 priv->r->set_static_move_action(port, false);
1181
1182 mutex_unlock(&priv->reg_mutex);
1183
1184 return 0;
1185 }
1186
1187 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1188 struct net_device *bridge)
1189 {
1190 struct rtl838x_switch_priv *priv = ds->priv;
1191 u64 port_bitmap = 0, v;
1192
1193 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1194 mutex_lock(&priv->reg_mutex);
1195 for (int i = 0; i < ds->num_ports; i++) {
1196 /* Remove this port from the port matrix of the other ports
1197 * in the same bridge. If the port is disabled, port matrix
1198 * is kept and not being setup until the port becomes enabled.
1199 * And the other port's port matrix cannot be broken when the
1200 * other port is still a VLAN-aware port.
1201 */
1202 if (dsa_is_user_port(ds, i) && i != port) {
1203 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1204 continue;
1205 if (priv->ports[i].enable)
1206 priv->r->traffic_disable(i, port);
1207
1208 priv->ports[i].pm &= ~BIT_ULL(port);
1209 port_bitmap |= BIT_ULL(i);
1210 }
1211 }
1212
1213 /* Remove all other ports from this port matrix. */
1214 if (priv->ports[port].enable) {
1215 v = priv->r->traffic_get(port);
1216 v &= ~port_bitmap;
1217 priv->r->traffic_set(port, v);
1218 }
1219 priv->ports[port].pm &= ~port_bitmap;
1220
1221 if (priv->r->set_static_move_action)
1222 priv->r->set_static_move_action(port, true);
1223
1224 mutex_unlock(&priv->reg_mutex);
1225 }
1226
1227 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1228 {
1229 u32 msti = 0;
1230 u32 port_state[4];
1231 int index, bit;
1232 int pos = port;
1233 struct rtl838x_switch_priv *priv = ds->priv;
1234 int n = priv->port_width << 1;
1235
1236 /* Ports above or equal CPU port can never be configured */
1237 if (port >= priv->cpu_port)
1238 return;
1239
1240 mutex_lock(&priv->reg_mutex);
1241
1242 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1243 * have 64 bit fields, 839x and 931x have 128 bit fields
1244 */
1245 if (priv->family_id == RTL8390_FAMILY_ID)
1246 pos += 12;
1247 if (priv->family_id == RTL9300_FAMILY_ID)
1248 pos += 3;
1249 if (priv->family_id == RTL9310_FAMILY_ID)
1250 pos += 8;
1251
1252 index = n - (pos >> 4) - 1;
1253 bit = (pos << 1) % 32;
1254
1255 priv->r->stp_get(priv, msti, port_state);
1256
1257 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1258 port_state[index] &= ~(3 << bit);
1259
1260 switch (state) {
1261 case BR_STATE_DISABLED: /* 0 */
1262 port_state[index] |= (0 << bit);
1263 break;
1264 case BR_STATE_BLOCKING: /* 4 */
1265 case BR_STATE_LISTENING: /* 1 */
1266 port_state[index] |= (1 << bit);
1267 break;
1268 case BR_STATE_LEARNING: /* 2 */
1269 port_state[index] |= (2 << bit);
1270 break;
1271 case BR_STATE_FORWARDING: /* 3 */
1272 port_state[index] |= (3 << bit);
1273 default:
1274 break;
1275 }
1276
1277 priv->r->stp_set(priv, msti, port_state);
1278
1279 mutex_unlock(&priv->reg_mutex);
1280 }
1281
1282 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1283 {
1284 struct rtl838x_switch_priv *priv = ds->priv;
1285 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1286
1287 pr_debug("FAST AGE port %d\n", port);
1288 mutex_lock(&priv->reg_mutex);
1289 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1290 * port fields:
1291 * 0-4: Replacing port
1292 * 5-9: Flushed/replaced port
1293 * 10-21: FVID
1294 * 22: Entry types: 1: dynamic, 0: also static
1295 * 23: Match flush port
1296 * 24: Match FVID
1297 * 25: Flush (0) or replace (1) L2 entries
1298 * 26: Status of action (1: Start, 0: Done)
1299 */
1300 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1301
1302 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1303
1304 mutex_unlock(&priv->reg_mutex);
1305 }
1306
1307 void rtl931x_fast_age(struct dsa_switch *ds, int port)
1308 {
1309 struct rtl838x_switch_priv *priv = ds->priv;
1310
1311 pr_info("%s port %d\n", __func__, port);
1312 mutex_lock(&priv->reg_mutex);
1313 sw_w32(port << 11, RTL931X_L2_TBL_FLUSH_CTRL + 4);
1314
1315 sw_w32(BIT(24) | BIT(28), RTL931X_L2_TBL_FLUSH_CTRL);
1316
1317 do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
1318
1319 mutex_unlock(&priv->reg_mutex);
1320 }
1321
1322 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1323 {
1324 struct rtl838x_switch_priv *priv = ds->priv;
1325
1326 if (priv->family_id == RTL9310_FAMILY_ID)
1327 return rtl931x_fast_age(ds, port);
1328
1329 pr_debug("FAST AGE port %d\n", port);
1330 mutex_lock(&priv->reg_mutex);
1331 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1332
1333 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1334
1335 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1336
1337 mutex_unlock(&priv->reg_mutex);
1338 }
1339
1340 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1341 bool vlan_filtering,
1342 struct netlink_ext_ack *extack)
1343 {
1344 struct rtl838x_switch_priv *priv = ds->priv;
1345
1346 pr_debug("%s: port %d\n", __func__, port);
1347 mutex_lock(&priv->reg_mutex);
1348
1349 if (vlan_filtering) {
1350 /* Enable ingress and egress filtering
1351 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1352 * the filter action:
1353 * 0: Always Forward
1354 * 1: Drop packet
1355 * 2: Trap packet to CPU port
1356 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1357 */
1358 if (port != priv->cpu_port)
1359 priv->r->set_vlan_igr_filter(port, IGR_DROP);
1360
1361 priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
1362 } else {
1363 /* Disable ingress and egress filtering */
1364 if (port != priv->cpu_port)
1365 priv->r->set_vlan_igr_filter(port, IGR_FORWARD);
1366
1367 priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
1368 }
1369
1370 /* Do we need to do something to the CPU-Port, too? */
1371 mutex_unlock(&priv->reg_mutex);
1372
1373 return 0;
1374 }
1375
1376 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1377 const struct switchdev_obj_port_vlan *vlan)
1378 {
1379 struct rtl838x_vlan_info info;
1380 struct rtl838x_switch_priv *priv = ds->priv;
1381
1382 priv->r->vlan_tables_read(0, &info);
1383
1384 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1385 info.tagged_ports, info.untagged_ports, info.profile_id,
1386 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1387
1388 priv->r->vlan_tables_read(1, &info);
1389 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1390 info.tagged_ports, info.untagged_ports, info.profile_id,
1391 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1392 priv->r->vlan_set_untagged(1, info.untagged_ports);
1393 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1394
1395 priv->r->vlan_set_tagged(1, &info);
1396 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1397
1398 return 0;
1399 }
1400
1401 static void rtl83xx_vlan_set_pvid(struct rtl838x_switch_priv *priv,
1402 int port, int pvid)
1403 {
1404 /* Set both inner and outer PVID of the port */
1405 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_INNER, pvid);
1406 priv->r->vlan_port_pvid_set(port, PBVLAN_TYPE_OUTER, pvid);
1407 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_INNER,
1408 PBVLAN_MODE_UNTAG_AND_PRITAG);
1409 priv->r->vlan_port_pvidmode_set(port, PBVLAN_TYPE_OUTER,
1410 PBVLAN_MODE_UNTAG_AND_PRITAG);
1411
1412 priv->ports[port].pvid = pvid;
1413 }
1414
1415 static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1416 const struct switchdev_obj_port_vlan *vlan,
1417 struct netlink_ext_ack *extack)
1418 {
1419 struct rtl838x_vlan_info info;
1420 struct rtl838x_switch_priv *priv = ds->priv;
1421 int err;
1422
1423 pr_debug("%s port %d, vid %d, flags %x\n",
1424 __func__, port, vlan->vid, vlan->flags);
1425
1426 if (vlan->vid > 4095) {
1427 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1428 return -ENOTSUPP;
1429 }
1430
1431 err = rtl83xx_vlan_prepare(ds, port, vlan);
1432 if (err)
1433 return err;
1434
1435 mutex_lock(&priv->reg_mutex);
1436
1437 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1438 rtl83xx_vlan_set_pvid(priv, port, vlan->vid);
1439 else if (priv->ports[port].pvid == vlan->vid)
1440 rtl83xx_vlan_set_pvid(priv, port, 0);
1441
1442 /* Get port memberships of this vlan */
1443 priv->r->vlan_tables_read(vlan->vid, &info);
1444
1445 /* new VLAN? */
1446 if (!info.tagged_ports) {
1447 info.fid = 0;
1448 info.hash_mc_fid = false;
1449 info.hash_uc_fid = false;
1450 info.profile_id = 0;
1451 }
1452
1453 /* sanitize untagged_ports - must be a subset */
1454 if (info.untagged_ports & ~info.tagged_ports)
1455 info.untagged_ports = 0;
1456
1457 info.tagged_ports |= BIT_ULL(port);
1458 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1459 info.untagged_ports |= BIT_ULL(port);
1460 else
1461 info.untagged_ports &= ~BIT_ULL(port);
1462
1463 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1464 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1465
1466 priv->r->vlan_set_tagged(vlan->vid, &info);
1467 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1468
1469 mutex_unlock(&priv->reg_mutex);
1470
1471 return 0;
1472 }
1473
1474 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1475 const struct switchdev_obj_port_vlan *vlan)
1476 {
1477 struct rtl838x_vlan_info info;
1478 struct rtl838x_switch_priv *priv = ds->priv;
1479 u16 pvid;
1480
1481 pr_debug("%s: port %d, vid %d, flags %x\n",
1482 __func__, port, vlan->vid, vlan->flags);
1483
1484 if (vlan->vid > 4095) {
1485 dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
1486 return -ENOTSUPP;
1487 }
1488
1489 mutex_lock(&priv->reg_mutex);
1490 pvid = priv->ports[port].pvid;
1491
1492 /* Reset to default if removing the current PVID */
1493 if (vlan->vid == pvid) {
1494 rtl83xx_vlan_set_pvid(priv, port, 0);
1495 }
1496 /* Get port memberships of this vlan */
1497 priv->r->vlan_tables_read(vlan->vid, &info);
1498
1499 /* remove port from both tables */
1500 info.untagged_ports &= (~BIT_ULL(port));
1501 info.tagged_ports &= (~BIT_ULL(port));
1502
1503 priv->r->vlan_set_untagged(vlan->vid, info.untagged_ports);
1504 pr_debug("Untagged ports, VLAN %d: %llx\n", vlan->vid, info.untagged_ports);
1505
1506 priv->r->vlan_set_tagged(vlan->vid, &info);
1507 pr_debug("Tagged ports, VLAN %d: %llx\n", vlan->vid, info.tagged_ports);
1508
1509 mutex_unlock(&priv->reg_mutex);
1510
1511 return 0;
1512 }
1513
1514 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1515 {
1516 memset(e, 0, sizeof(*e));
1517
1518 e->type = L2_UNICAST;
1519 e->valid = true;
1520
1521 e->age = 3;
1522 e->is_static = true;
1523
1524 e->port = port;
1525
1526 e->rvid = e->vid = vid;
1527 e->is_ip_mc = e->is_ipv6_mc = false;
1528 u64_to_ether_addr(mac, e->mac);
1529 }
1530
1531 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1532 {
1533 memset(e, 0, sizeof(*e));
1534
1535 e->type = L2_MULTICAST;
1536 e->valid = true;
1537
1538 e->mc_portmask_index = mc_group;
1539
1540 e->rvid = e->vid = vid;
1541 e->is_ip_mc = e->is_ipv6_mc = false;
1542 u64_to_ether_addr(mac, e->mac);
1543 }
1544
1545 /* Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1546 * over the entries in the bucket until either a matching entry is found or an empty slot
1547 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1548 * when an empty slot was found and must exist is false, the index of the slot is returned
1549 * when no slots are available returns -1
1550 */
1551 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1552 bool must_exist, struct rtl838x_l2_entry *e)
1553 {
1554 int idx = -1;
1555 u32 key = priv->r->l2_hash_key(priv, seed);
1556 u64 entry;
1557
1558 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1559 /* Loop over all entries in the hash-bucket and over the second block on 93xx SoCs */
1560 for (int i = 0; i < priv->l2_bucket_size; i++) {
1561 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1562 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1563 if (must_exist && !e->valid)
1564 continue;
1565 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1566 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1567 break;
1568 }
1569 }
1570
1571 return idx;
1572 }
1573
1574 /* Uses the seed to identify an entry in the CAM by looping over all its entries
1575 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1576 * when an empty slot was found the index of the slot is returned
1577 * when no slots are available returns -1
1578 */
1579 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1580 bool must_exist, struct rtl838x_l2_entry *e)
1581 {
1582 int idx = -1;
1583 u64 entry;
1584
1585 for (int i = 0; i < 64; i++) {
1586 entry = priv->r->read_cam(i, e);
1587 if (!must_exist && !e->valid) {
1588 if (idx < 0) /* First empty entry? */
1589 idx = i;
1590 break;
1591 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1592 pr_debug("Found entry in CAM\n");
1593 idx = i;
1594 break;
1595 }
1596 }
1597
1598 return idx;
1599 }
1600
1601 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1602 const unsigned char *addr, u16 vid)
1603 {
1604 struct rtl838x_switch_priv *priv = ds->priv;
1605 u64 mac = ether_addr_to_u64(addr);
1606 struct rtl838x_l2_entry e;
1607 int err = 0, idx;
1608 u64 seed = priv->r->l2_hash_seed(mac, vid);
1609
1610 if (priv->is_lagmember[port]) {
1611 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1612 return 0;
1613 }
1614
1615 mutex_lock(&priv->reg_mutex);
1616
1617 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1618
1619 /* Found an existing or empty entry */
1620 if (idx >= 0) {
1621 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1622 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1623 goto out;
1624 }
1625
1626 /* Hash buckets full, try CAM */
1627 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1628
1629 if (idx >= 0) {
1630 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1631 priv->r->write_cam(idx, &e);
1632 goto out;
1633 }
1634
1635 err = -ENOTSUPP;
1636
1637 out:
1638 mutex_unlock(&priv->reg_mutex);
1639
1640 return err;
1641 }
1642
1643 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1644 const unsigned char *addr, u16 vid)
1645 {
1646 struct rtl838x_switch_priv *priv = ds->priv;
1647 u64 mac = ether_addr_to_u64(addr);
1648 struct rtl838x_l2_entry e;
1649 int err = 0, idx;
1650 u64 seed = priv->r->l2_hash_seed(mac, vid);
1651
1652 pr_debug("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1653 mutex_lock(&priv->reg_mutex);
1654
1655 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1656
1657 if (idx >= 0) {
1658 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1659 e.valid = false;
1660 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1661 goto out;
1662 }
1663
1664 /* Check CAM for spillover from hash buckets */
1665 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1666
1667 if (idx >= 0) {
1668 e.valid = false;
1669 priv->r->write_cam(idx, &e);
1670 goto out;
1671 }
1672 err = -ENOENT;
1673
1674 out:
1675 mutex_unlock(&priv->reg_mutex);
1676
1677 return err;
1678 }
1679
1680 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1681 dsa_fdb_dump_cb_t *cb, void *data)
1682 {
1683 struct rtl838x_l2_entry e;
1684 struct rtl838x_switch_priv *priv = ds->priv;
1685
1686 mutex_lock(&priv->reg_mutex);
1687
1688 for (int i = 0; i < priv->fib_entries; i++) {
1689 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1690
1691 if (!e.valid)
1692 continue;
1693
1694 if (e.port == port || e.port == RTL930X_PORT_IGNORE)
1695 cb(e.mac, e.vid, e.is_static, data);
1696
1697 if (!((i + 1) % 64))
1698 cond_resched();
1699 }
1700
1701 for (int i = 0; i < 64; i++) {
1702 priv->r->read_cam(i, &e);
1703
1704 if (!e.valid)
1705 continue;
1706
1707 if (e.port == port)
1708 cb(e.mac, e.vid, e.is_static, data);
1709 }
1710
1711 mutex_unlock(&priv->reg_mutex);
1712
1713 return 0;
1714 }
1715
1716 static int rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1717 const struct switchdev_obj_port_mdb *mdb)
1718 {
1719 struct rtl838x_switch_priv *priv = ds->priv;
1720 u64 mac = ether_addr_to_u64(mdb->addr);
1721 struct rtl838x_l2_entry e;
1722 int err = 0, idx;
1723 int vid = mdb->vid;
1724 u64 seed = priv->r->l2_hash_seed(mac, vid);
1725 int mc_group;
1726
1727 if (priv->id >= 0x9300)
1728 return -EOPNOTSUPP;
1729
1730 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1731
1732 if (priv->is_lagmember[port]) {
1733 pr_debug("%s: %d is lag slave. ignore\n", __func__, port);
1734 return -EINVAL;
1735 }
1736
1737 mutex_lock(&priv->reg_mutex);
1738
1739 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1740
1741 /* Found an existing or empty entry */
1742 if (idx >= 0) {
1743 if (e.valid) {
1744 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1745 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1746 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1747 } else {
1748 pr_debug("New entry for seed %016llx\n", seed);
1749 mc_group = rtl83xx_mc_group_alloc(priv, port);
1750 if (mc_group < 0) {
1751 err = -ENOTSUPP;
1752 goto out;
1753 }
1754 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1755 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1756 }
1757 goto out;
1758 }
1759
1760 /* Hash buckets full, try CAM */
1761 idx = rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1762
1763 if (idx >= 0) {
1764 if (e.valid) {
1765 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1766 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1767 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1768 } else {
1769 pr_debug("New entry\n");
1770 mc_group = rtl83xx_mc_group_alloc(priv, port);
1771 if (mc_group < 0) {
1772 err = -ENOTSUPP;
1773 goto out;
1774 }
1775 rtl83xx_setup_l2_mc_entry(&e, vid, mac, mc_group);
1776 priv->r->write_cam(idx, &e);
1777 }
1778 goto out;
1779 }
1780
1781 err = -ENOTSUPP;
1782
1783 out:
1784 mutex_unlock(&priv->reg_mutex);
1785 if (err)
1786 dev_err(ds->dev, "failed to add MDB entry\n");
1787
1788 return err;
1789 }
1790
1791 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1792 const struct switchdev_obj_port_mdb *mdb)
1793 {
1794 struct rtl838x_switch_priv *priv = ds->priv;
1795 u64 mac = ether_addr_to_u64(mdb->addr);
1796 struct rtl838x_l2_entry e;
1797 int err = 0, idx;
1798 int vid = mdb->vid;
1799 u64 seed = priv->r->l2_hash_seed(mac, vid);
1800 u64 portmask;
1801
1802 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1803
1804 if (priv->is_lagmember[port]) {
1805 pr_info("%s: %d is lag slave. ignore\n", __func__, port);
1806 return 0;
1807 }
1808
1809 mutex_lock(&priv->reg_mutex);
1810
1811 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1812
1813 if (idx >= 0) {
1814 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1815 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1816 if (!portmask) {
1817 e.valid = false;
1818 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1819 }
1820 goto out;
1821 }
1822
1823 /* Check CAM for spillover from hash buckets */
1824 idx = rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1825
1826 if (idx >= 0) {
1827 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1828 if (!portmask) {
1829 e.valid = false;
1830 priv->r->write_cam(idx, &e);
1831 }
1832 goto out;
1833 }
1834 /* TODO: Re-enable with a newer kernel: err = -ENOENT; */
1835
1836 out:
1837 mutex_unlock(&priv->reg_mutex);
1838
1839 return err;
1840 }
1841
1842 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1843 struct dsa_mall_mirror_tc_entry *mirror,
1844 bool ingress)
1845 {
1846 /* We support 4 mirror groups, one destination port per group */
1847 int group;
1848 struct rtl838x_switch_priv *priv = ds->priv;
1849 int ctrl_reg, dpm_reg, spm_reg;
1850
1851 pr_debug("In %s\n", __func__);
1852
1853 for (group = 0; group < 4; group++) {
1854 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1855 break;
1856 }
1857 if (group >= 4) {
1858 for (group = 0; group < 4; group++) {
1859 if (priv->mirror_group_ports[group] < 0)
1860 break;
1861 }
1862 }
1863
1864 if (group >= 4)
1865 return -ENOSPC;
1866
1867 ctrl_reg = priv->r->mir_ctrl + group * 4;
1868 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1869 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1870
1871 pr_debug("Using group %d\n", group);
1872 mutex_lock(&priv->reg_mutex);
1873
1874 if (priv->family_id == RTL8380_FAMILY_ID) {
1875 /* Enable mirroring to port across VLANs (bit 11) */
1876 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1877 } else {
1878 /* Enable mirroring to destination port */
1879 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1880 }
1881
1882 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1883 mutex_unlock(&priv->reg_mutex);
1884 return -EEXIST;
1885 }
1886 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1887 mutex_unlock(&priv->reg_mutex);
1888 return -EEXIST;
1889 }
1890
1891 if (ingress)
1892 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1893 else
1894 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1895
1896 priv->mirror_group_ports[group] = mirror->to_local_port;
1897 mutex_unlock(&priv->reg_mutex);
1898
1899 return 0;
1900 }
1901
1902 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1903 struct dsa_mall_mirror_tc_entry *mirror)
1904 {
1905 int group = 0;
1906 struct rtl838x_switch_priv *priv = ds->priv;
1907 int ctrl_reg, dpm_reg, spm_reg;
1908
1909 pr_debug("In %s\n", __func__);
1910 for (group = 0; group < 4; group++) {
1911 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1912 break;
1913 }
1914 if (group >= 4)
1915 return;
1916
1917 ctrl_reg = priv->r->mir_ctrl + group * 4;
1918 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1919 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1920
1921 mutex_lock(&priv->reg_mutex);
1922 if (mirror->ingress) {
1923 /* Ingress, clear source port matrix */
1924 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1925 } else {
1926 /* Egress, clear destination port matrix */
1927 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1928 }
1929
1930 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1931 priv->mirror_group_ports[group] = -1;
1932 sw_w32(0, ctrl_reg);
1933 }
1934
1935 mutex_unlock(&priv->reg_mutex);
1936 }
1937
1938 static int rtl83xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1939 {
1940 struct rtl838x_switch_priv *priv = ds->priv;
1941 unsigned long features = 0;
1942 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1943 if (priv->r->enable_learning)
1944 features |= BR_LEARNING;
1945 if (priv->r->enable_flood)
1946 features |= BR_FLOOD;
1947 if (priv->r->enable_mcast_flood)
1948 features |= BR_MCAST_FLOOD;
1949 if (priv->r->enable_bcast_flood)
1950 features |= BR_BCAST_FLOOD;
1951 if (flags.mask & ~(features))
1952 return -EINVAL;
1953
1954 return 0;
1955 }
1956
1957 static int rtl83xx_port_bridge_flags(struct dsa_switch *ds, int port, struct switchdev_brport_flags flags, struct netlink_ext_ack *extack)
1958 {
1959 struct rtl838x_switch_priv *priv = ds->priv;
1960
1961 pr_debug("%s: %d %lX\n", __func__, port, flags.val);
1962 if (priv->r->enable_learning && (flags.mask & BR_LEARNING))
1963 priv->r->enable_learning(port, !!(flags.val & BR_LEARNING));
1964
1965 if (priv->r->enable_flood && (flags.mask & BR_FLOOD))
1966 priv->r->enable_flood(port, !!(flags.val & BR_FLOOD));
1967
1968 if (priv->r->enable_mcast_flood && (flags.mask & BR_MCAST_FLOOD))
1969 priv->r->enable_mcast_flood(port, !!(flags.val & BR_MCAST_FLOOD));
1970
1971 if (priv->r->enable_bcast_flood && (flags.mask & BR_BCAST_FLOOD))
1972 priv->r->enable_bcast_flood(port, !!(flags.val & BR_BCAST_FLOOD));
1973
1974 return 0;
1975 }
1976
1977 static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
1978 struct net_device *lag,
1979 struct netdev_lag_upper_info *info)
1980 {
1981 int id;
1982
1983 id = dsa_lag_id(ds->dst, lag);
1984 if (id < 0 || id >= ds->num_lag_ids)
1985 return false;
1986
1987 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
1988 return false;
1989 }
1990 if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
1991 return false;
1992
1993 return true;
1994 }
1995
1996 static int rtl83xx_port_lag_change(struct dsa_switch *ds, int port)
1997 {
1998 pr_debug("%s: %d\n", __func__, port);
1999 /* Nothing to be done... */
2000
2001 return 0;
2002 }
2003
2004 static int rtl83xx_port_lag_join(struct dsa_switch *ds, int port,
2005 struct net_device *lag,
2006 struct netdev_lag_upper_info *info)
2007 {
2008 struct rtl838x_switch_priv *priv = ds->priv;
2009 int i, err = 0;
2010
2011 if (!rtl83xx_lag_can_offload(ds, lag, info))
2012 return -EOPNOTSUPP;
2013
2014 mutex_lock(&priv->reg_mutex);
2015
2016 for (i = 0; i < priv->n_lags; i++) {
2017 if ((!priv->lag_devs[i]) || (priv->lag_devs[i] == lag))
2018 break;
2019 }
2020 if (port >= priv->cpu_port) {
2021 err = -EINVAL;
2022 goto out;
2023 }
2024 pr_info("port_lag_join: group %d, port %d\n",i, port);
2025 if (!priv->lag_devs[i])
2026 priv->lag_devs[i] = lag;
2027
2028 if (priv->lag_primary[i] == -1) {
2029 priv->lag_primary[i] = port;
2030 } else
2031 priv->is_lagmember[port] = 1;
2032
2033 priv->lagmembers |= (1ULL << port);
2034
2035 pr_debug("lag_members = %llX\n", priv->lagmembers);
2036 err = rtl83xx_lag_add(priv->ds, i, port, info);
2037 if (err) {
2038 err = -EINVAL;
2039 goto out;
2040 }
2041
2042 out:
2043 mutex_unlock(&priv->reg_mutex);
2044
2045 return err;
2046 }
2047
2048 static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
2049 struct net_device *lag)
2050 {
2051 int i, group = -1, err;
2052 struct rtl838x_switch_priv *priv = ds->priv;
2053
2054 mutex_lock(&priv->reg_mutex);
2055 for (i = 0; i < priv->n_lags; i++) {
2056 if (priv->lags_port_members[i] & BIT_ULL(port)) {
2057 group = i;
2058 break;
2059 }
2060 }
2061
2062 if (group == -1) {
2063 pr_info("port_lag_leave: port %d is not a member\n", port);
2064 err = -EINVAL;
2065 goto out;
2066 }
2067
2068 if (port >= priv->cpu_port) {
2069 err = -EINVAL;
2070 goto out;
2071 }
2072 pr_info("port_lag_del: group %d, port %d\n",group, port);
2073 priv->lagmembers &=~ (1ULL << port);
2074 priv->lag_primary[i] = -1;
2075 priv->is_lagmember[port] = 0;
2076 pr_debug("lag_members = %llX\n", priv->lagmembers);
2077 err = rtl83xx_lag_del(priv->ds, group, port);
2078 if (err) {
2079 err = -EINVAL;
2080 goto out;
2081 }
2082 if (!priv->lags_port_members[i])
2083 priv->lag_devs[i] = NULL;
2084
2085 out:
2086 mutex_unlock(&priv->reg_mutex);
2087 return 0;
2088 }
2089
2090 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
2091 {
2092 u32 val;
2093 u32 offset = 0;
2094 struct rtl838x_switch_priv *priv = ds->priv;
2095
2096 if ((phy_addr >= 24) &&
2097 (phy_addr <= 27) &&
2098 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2099 if (phy_addr == 26)
2100 offset = 0x100;
2101 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
2102 return val;
2103 }
2104
2105 read_phy(phy_addr, 0, phy_reg, &val);
2106 return val;
2107 }
2108
2109 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
2110 {
2111 u32 offset = 0;
2112 struct rtl838x_switch_priv *priv = ds->priv;
2113
2114 if ((phy_addr >= 24) &&
2115 (phy_addr <= 27) &&
2116 (priv->ports[24].phy == PHY_RTL838X_SDS)) {
2117 if (phy_addr == 26)
2118 offset = 0x100;
2119 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
2120 return 0;
2121 }
2122 return write_phy(phy_addr, 0, phy_reg, val);
2123 }
2124
2125 const struct dsa_switch_ops rtl83xx_switch_ops = {
2126 .get_tag_protocol = rtl83xx_get_tag_protocol,
2127 .setup = rtl83xx_setup,
2128
2129 .phy_read = dsa_phy_read,
2130 .phy_write = dsa_phy_write,
2131
2132 .phylink_validate = rtl83xx_phylink_validate,
2133 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
2134 .phylink_mac_config = rtl83xx_phylink_mac_config,
2135 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
2136 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
2137
2138 .get_strings = rtl83xx_get_strings,
2139 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2140 .get_sset_count = rtl83xx_get_sset_count,
2141
2142 .port_enable = rtl83xx_port_enable,
2143 .port_disable = rtl83xx_port_disable,
2144
2145 .get_mac_eee = rtl83xx_get_mac_eee,
2146 .set_mac_eee = rtl83xx_set_mac_eee,
2147
2148 .set_ageing_time = rtl83xx_set_ageing_time,
2149 .port_bridge_join = rtl83xx_port_bridge_join,
2150 .port_bridge_leave = rtl83xx_port_bridge_leave,
2151 .port_stp_state_set = rtl83xx_port_stp_state_set,
2152 .port_fast_age = rtl83xx_fast_age,
2153
2154 .port_vlan_filtering = rtl83xx_vlan_filtering,
2155 .port_vlan_add = rtl83xx_vlan_add,
2156 .port_vlan_del = rtl83xx_vlan_del,
2157
2158 .port_fdb_add = rtl83xx_port_fdb_add,
2159 .port_fdb_del = rtl83xx_port_fdb_del,
2160 .port_fdb_dump = rtl83xx_port_fdb_dump,
2161
2162 .port_mdb_add = rtl83xx_port_mdb_add,
2163 .port_mdb_del = rtl83xx_port_mdb_del,
2164
2165 .port_mirror_add = rtl83xx_port_mirror_add,
2166 .port_mirror_del = rtl83xx_port_mirror_del,
2167
2168 .port_lag_change = rtl83xx_port_lag_change,
2169 .port_lag_join = rtl83xx_port_lag_join,
2170 .port_lag_leave = rtl83xx_port_lag_leave,
2171
2172 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2173 .port_bridge_flags = rtl83xx_port_bridge_flags,
2174 };
2175
2176 const struct dsa_switch_ops rtl930x_switch_ops = {
2177 .get_tag_protocol = rtl83xx_get_tag_protocol,
2178 .setup = rtl93xx_setup,
2179
2180 .phy_read = dsa_phy_read,
2181 .phy_write = dsa_phy_write,
2182
2183 .phylink_validate = rtl93xx_phylink_validate,
2184 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
2185 .phylink_mac_config = rtl93xx_phylink_mac_config,
2186 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
2187 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
2188
2189 .get_strings = rtl83xx_get_strings,
2190 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
2191 .get_sset_count = rtl83xx_get_sset_count,
2192
2193 .port_enable = rtl83xx_port_enable,
2194 .port_disable = rtl83xx_port_disable,
2195
2196 .get_mac_eee = rtl93xx_get_mac_eee,
2197 .set_mac_eee = rtl83xx_set_mac_eee,
2198
2199 .set_ageing_time = rtl83xx_set_ageing_time,
2200 .port_bridge_join = rtl83xx_port_bridge_join,
2201 .port_bridge_leave = rtl83xx_port_bridge_leave,
2202 .port_stp_state_set = rtl83xx_port_stp_state_set,
2203 .port_fast_age = rtl930x_fast_age,
2204
2205 .port_vlan_filtering = rtl83xx_vlan_filtering,
2206 .port_vlan_add = rtl83xx_vlan_add,
2207 .port_vlan_del = rtl83xx_vlan_del,
2208
2209 .port_fdb_add = rtl83xx_port_fdb_add,
2210 .port_fdb_del = rtl83xx_port_fdb_del,
2211 .port_fdb_dump = rtl83xx_port_fdb_dump,
2212
2213 .port_mdb_add = rtl83xx_port_mdb_add,
2214 .port_mdb_del = rtl83xx_port_mdb_del,
2215
2216 .port_lag_change = rtl83xx_port_lag_change,
2217 .port_lag_join = rtl83xx_port_lag_join,
2218 .port_lag_leave = rtl83xx_port_lag_leave,
2219
2220 .port_pre_bridge_flags = rtl83xx_port_pre_bridge_flags,
2221 .port_bridge_flags = rtl83xx_port_bridge_flags,
2222 };
OpenWrt Source Repository