mediatek: convert to new LED color/function format where possible
[openwrt/openwrt.git] / target / linux / mediatek / dts / mt7622-xiaomi-redmi-router-ax6s.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/gpio/gpio.h>
7
8 #include "mt7622.dtsi"
9 #include "mt6380.dtsi"
10
11 / {
12 model = "Xiaomi Redmi Router AX6S";
13 compatible = "xiaomi,redmi-router-ax6s", "mediatek,mt7622";
14
15 aliases {
16 serial0 = &uart0;
17 led-boot = &led_power_amber;
18 led-failsafe = &led_power_amber;
19 led-running = &led_power_blue;
20 led-upgrade = &led_power_blue;
21 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
26 };
27
28 memory {
29 reg = <0 0x40000000 0 0x8000000>;
30 };
31
32 leds {
33 compatible = "gpio-leds";
34
35 led_power_blue: power_blue {
36 function = LED_FUNCTION_POWER;
37 color = <LED_COLOR_ID_BLUE>;
38 gpios = <&pio 18 GPIO_ACTIVE_LOW>;
39 };
40
41 led_power_amber: power_amber {
42 function = LED_FUNCTION_POWER;
43 color = <LED_COLOR_ID_AMBER>;
44 gpios = <&pio 17 GPIO_ACTIVE_LOW>;
45 };
46
47 led_net_blue: net_blue {
48 label = "blue:net";
49 gpios = <&pio 01 GPIO_ACTIVE_LOW>;
50 };
51
52 led_net_amber: net_amber {
53 label = "amber:net";
54 gpios = <&pio 16 GPIO_ACTIVE_LOW>;
55 };
56
57 };
58
59 keys {
60 compatible = "gpio-keys";
61
62 reset {
63 label = "reset";
64 gpios = <&pio 0 GPIO_ACTIVE_LOW>;
65 linux,code = <KEY_RESTART>;
66 };
67
68 mesh {
69 label = "mesh";
70 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
71 linux,code = <BTN_9>;
72 linux,input-type = <EV_SW>;
73 };
74 };
75 };
76
77 &cpu0 {
78 proc-supply = <&mt6380_vcpu_reg>;
79 sram-supply = <&mt6380_vm_reg>;
80 };
81
82 &cpu1 {
83 proc-supply = <&mt6380_vcpu_reg>;
84 sram-supply = <&mt6380_vm_reg>;
85 };
86
87 &pio {
88 eth_pins: eth-pins {
89 mux {
90 function = "eth";
91 groups = "mdc_mdio", "rgmii_via_gmac2";
92 };
93 };
94
95 pcie0_pins: pcie0-pins {
96 mux {
97 function = "pcie";
98 groups = "pcie0_pad_perst",
99 "pcie0_1_waken",
100 "pcie0_1_clkreq";
101 };
102 };
103
104 pmic_bus_pins: pmic-bus-pins {
105 mux {
106 function = "pmic";
107 groups = "pmic_bus";
108 };
109 };
110
111 pwm7_pins: pwm1-2-pins {
112 mux {
113 function = "pwm";
114 groups = "pwm_ch7_2";
115 };
116 };
117
118 /* Serial NAND is shared pin with SPI-NOR */
119 serial_nand_pins: serial-nand-pins {
120 mux {
121 function = "flash";
122 groups = "snfi";
123 };
124 };
125
126 uart0_pins: uart0-pins {
127 mux {
128 function = "uart";
129 groups = "uart0_0_tx_rx" ;
130 };
131 };
132
133 watchdog_pins: watchdog-pins {
134 mux {
135 function = "watchdog";
136 groups = "watchdog";
137 };
138 };
139 };
140
141 &eth {
142 pinctrl-names = "default";
143 pinctrl-0 = <&eth_pins>;
144 status = "okay";
145
146 gmac0: mac@0 {
147 compatible = "mediatek,eth-mac";
148 reg = <0>;
149
150 phy-connection-type = "2500base-x";
151
152 nvmem-cells = <&macaddr_factory_4 (-1)>;
153 nvmem-cell-names = "mac-address";
154
155 fixed-link {
156 speed = <2500>;
157 full-duplex;
158 pause;
159 };
160 };
161
162 mdio-bus {
163 #address-cells = <1>;
164 #size-cells = <0>;
165
166 switch@0 {
167 compatible = "mediatek,mt7531";
168 reg = <0>;
169 interrupt-controller;
170 #interrupt-cells = <1>;
171 interrupt-parent = <&pio>;
172 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
173 reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
174
175 ports {
176 #address-cells = <1>;
177 #size-cells = <0>;
178
179 wan: port@1 {
180 reg = <1>;
181 label = "wan";
182 };
183
184 port@2 {
185 reg = <2>;
186 label = "lan1";
187 };
188
189 port@3 {
190 reg = <3>;
191 label = "lan2";
192 };
193
194 port@4 {
195 reg = <4>;
196 label = "lan3";
197 };
198
199 port@6 {
200 reg = <6>;
201 ethernet = <&gmac0>;
202 phy-mode = "2500base-x";
203
204 fixed-link {
205 speed = <2500>;
206 full-duplex;
207 pause;
208 };
209 };
210 };
211 };
212 };
213 };
214
215 &bch {
216 status = "okay";
217 };
218
219 &snfi {
220 pinctrl-names = "default";
221 pinctrl-0 = <&serial_nand_pins>;
222 status = "okay";
223
224 flash@0 {
225 compatible = "spi-nand";
226 reg = <0>;
227 spi-tx-bus-width = <4>;
228 spi-rx-bus-width = <4>;
229 nand-ecc-engine = <&snfi>;
230
231 mediatek,bmt-v2;
232 mediatek,bmt-table-size = <0x1000>;
233 mediatek,bmt-remap-range = <0x0 0x6c0000>;
234
235 partitions {
236 compatible = "fixed-partitions";
237 #address-cells = <1>;
238 #size-cells = <1>;
239
240 partition@0 {
241 label = "Preloader";
242 reg = <0x0 0x80000>;
243 read-only;
244 };
245
246 partition@80000 {
247 label = "ATF";
248 reg = <0x80000 0x40000>;
249 read-only;
250 };
251
252 partition@c0000 {
253 label = "u-boot";
254 reg = <0xc0000 0x80000>;
255 read-only;
256 };
257
258 partition@140000 {
259 label = "u-boot-env";
260 reg = <0x140000 0x40000>;
261 };
262
263 partition@180000 {
264 label = "bdata";
265 reg = <0x180000 0x40000>;
266 };
267
268 factory: partition@1c0000 {
269 label = "factory";
270 reg = <0x1c0000 0x80000>;
271 read-only;
272
273 nvmem-layout {
274 compatible = "fixed-layout";
275 #address-cells = <1>;
276 #size-cells = <1>;
277
278 macaddr_factory_4: macaddr@4 {
279 compatible = "mac-base";
280 reg = <0x4 0x6>;
281 #nvmem-cell-cells = <1>;
282 };
283 };
284 };
285
286 partition@240000 {
287 label = "crash";
288 reg = <0x240000 0x40000>;
289 read-only;
290 };
291
292 partition@280000 {
293 label = "crash_log";
294 reg = <0x280000 0x40000>;
295 read-only;
296 };
297
298 /* Shrunk and renamed from "firmware"
299 * as to not break luci size checks
300 */
301 partition@2c0000 {
302 label = "kernel";
303 reg = <0x2c0000 0x400000>;
304 };
305
306 /* ubi partition is the result of squashing
307 * consecutive stock partitions:
308 * - firmware (partially)
309 * - firmware1
310 * - overlay
311 * - obr
312 */
313 partition@6c0000 {
314 label = "ubi";
315 reg = <0x6C0000 0x6f00000>;
316 };
317 };
318 };
319 };
320
321 &pcie0 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&pcie0_pins>;
324 status = "okay";
325 };
326
327 &slot0 {
328 status = "okay";
329
330 wifi@0,0 {
331 compatible = "mediatek,mt76";
332 reg = <0x0000 0 0 0 0>;
333 mediatek,mtd-eeprom = <&factory 0x5000>;
334 ieee80211-freq-limit = <5000000 6000000>;
335 mediatek,disable-radar-background;
336 };
337 };
338
339 &pwm {
340 pinctrl-names = "default";
341 pinctrl-0 = <&pwm7_pins>;
342 status = "okay";
343 };
344
345 &pwrap {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pmic_bus_pins>;
348 status = "okay";
349 };
350
351 &rtc {
352 status = "disabled";
353 };
354
355 &uart0 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&uart0_pins>;
358 status = "okay";
359 };
360
361 &watchdog {
362 pinctrl-names = "default";
363 pinctrl-0 = <&watchdog_pins>;
364 status = "okay";
365 };
366
367 &wmac {
368 status = "okay";
369
370 mediatek,mtd-eeprom = <&factory 0x0>;
371 };