3bb25695738bd2f89c3187eba0421f15738768f7
[openwrt/openwrt.git] / target / linux / brcm2708 / patches-4.14 / 950-0443-net-lan78xx-Support-auto-downshift-to-100Mb-s.patch
1 From 68502f802a66b68a6b5fefb52e709807a702a94b Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Mon, 26 Nov 2018 19:46:58 +0000
4 Subject: [PATCH 443/454] net: lan78xx: Support auto-downshift to 100Mb/s
5
6 Ethernet cables with faulty or missing pairs (specifically pairs C and
7 D) allow auto-negotiation to 1000Mbs, but do not support the successful
8 establishment of a link. Add a DT property, "microchip,downshift-after",
9 to configure the number of auto-negotiation failures after which it
10 falls back to 100Mbs. Valid values are 2, 3, 4, 5 and 0, where 0 means
11 never downshift.
12
13 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
14 ---
15 drivers/net/phy/microchip.c | 33 +++++++++++++++++++++++++++++++++
16 drivers/net/usb/lan78xx.c | 8 ++++++--
17 include/linux/microchipphy.h | 11 +++++++++++
18 3 files changed, 50 insertions(+), 2 deletions(-)
19
20 --- a/drivers/net/phy/microchip.c
21 +++ b/drivers/net/phy/microchip.c
22 @@ -21,6 +21,7 @@
23 #include <linux/phy.h>
24 #include <linux/microchipphy.h>
25 #include <linux/delay.h>
26 +#include <linux/of.h>
27
28 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
29 #define DRIVER_DESC "Microchip LAN88XX PHY driver"
30 @@ -225,6 +226,7 @@ static int lan88xx_probe(struct phy_devi
31 {
32 struct device *dev = &phydev->mdio.dev;
33 struct lan88xx_priv *priv;
34 + u32 downshift_after = 0;
35
36 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
37 if (!priv)
38 @@ -232,6 +234,37 @@ static int lan88xx_probe(struct phy_devi
39
40 priv->wolopts = 0;
41
42 + if (!of_property_read_u32(dev->of_node,
43 + "microchip,downshift-after",
44 + &downshift_after)) {
45 + u32 mask = LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK;
46 + u32 val = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
47 +
48 + switch (downshift_after) {
49 + case 2:
50 + val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2;
51 + break;
52 + case 3:
53 + val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3;
54 + break;
55 + case 4:
56 + val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4;
57 + break;
58 + case 5:
59 + val |= LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5;
60 + break;
61 + case 0:
62 + /* Disable completely */
63 + mask = LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT;
64 + val = 0;
65 + break;
66 + default:
67 + return -EINVAL;
68 + }
69 + (void)phy_modify_paged(phydev, 1, LAN78XX_PHY_CTRL3,
70 + mask, val);
71 + }
72 +
73 /* these values can be used to identify internal PHY */
74 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
75 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
76 --- a/drivers/net/usb/lan78xx.c
77 +++ b/drivers/net/usb/lan78xx.c
78 @@ -37,7 +37,8 @@
79 #include <linux/irq.h>
80 #include <linux/irqchip/chained_irq.h>
81 #include <linux/microchipphy.h>
82 -#include <linux/phy.h>
83 +#include <linux/phy_fixed.h>
84 +#include <linux/of_mdio.h>
85 #include <linux/of_net.h>
86 #include "lan78xx.h"
87
88 @@ -1768,6 +1769,7 @@ done:
89
90 static int lan78xx_mdio_init(struct lan78xx_net *dev)
91 {
92 + struct device_node *node;
93 int ret;
94
95 dev->mdiobus = mdiobus_alloc();
96 @@ -1797,7 +1799,9 @@ static int lan78xx_mdio_init(struct lan7
97 break;
98 }
99
100 - ret = mdiobus_register(dev->mdiobus);
101 + node = of_get_child_by_name(dev->udev->dev.of_node, "mdio");
102 + ret = of_mdiobus_register(dev->mdiobus, node);
103 + of_node_put(node);
104 if (ret) {
105 netdev_err(dev->net, "can't register MDIO bus\n");
106 goto exit1;
107 --- a/include/linux/microchipphy.h
108 +++ b/include/linux/microchipphy.h
109 @@ -70,6 +70,17 @@
110 #define LAN88XX_MMD3_CHIP_ID (32877)
111 #define LAN88XX_MMD3_CHIP_REV (32878)
112
113 +/* Registers specific to the LAN7800/LAN7850 embedded phy */
114 +#define LAN78XX_PHY_LED_MODE_SELECT (0x1D)
115 +
116 +#define LAN78XX_PHY_CTRL3 (0x14)
117 +#define LAN78XX_PHY_CTRL3_AUTO_DOWNSHIFT (0x0010)
118 +#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_MASK (0x000c)
119 +#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_2 (0x0000)
120 +#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_3 (0x0004)
121 +#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_4 (0x0008)
122 +#define LAN78XX_PHY_CTRL3_DOWNSHIFT_CTRL_5 (0x000c)
123 +
124 /* DSP registers */
125 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG (0x806A)
126 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_ (0x2000)