Merge changes I0355e084,I6a6dd1c0 into integration

* changes:
  mediatek: mt8183: add EMI MPU driver for DRAM protection
  mediatek: mt8183: add DEVAPC driver to control protection

diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h
new file mode 100644 (file)
index 0000000..0df34c9
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a65.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A65_H
+#define CORTEX_A65_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_A65_MIDR                        U(0x410FD060)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65_ECTLR_EL1           S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A65_CPUACTLR_EL1                S3_0_C15_C1_0
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+
+#define CORTEX_A65_CPUPWRCTLR_EL1      S3_0_C15_C2_7
+#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT       (U(1) << 0)
+
+#endif /* CORTEX_A65_H */

diff --git a/lib/cpus/aarch64/cortex_a65.S b/lib/cpus/aarch64/cortex_a65.S
new file mode 100644 (file)
index 0000000..666324c
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a65.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <cortex_a65.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if !HW_ASSISTED_COHERENCY
+#error "Cortex-A65 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS
+#error "Cortex-A65 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+/* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A65.
+ * Shall clobber: x0-x19
+ * -------------------------------------------------
+ */
+func cortex_a65_reset_func
+       mov     x19, x30
+
+#if ERRATA_DSU_936184
+       bl      errata_dsu_936184_wa
+#endif
+
+       ret     x19
+endfunc cortex_a65_reset_func
+
+func cortex_a65_cpu_pwr_dwn
+       mrs     x0, CORTEX_A65_CPUPWRCTLR_EL1
+       orr     x0, x0, #CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+       msr     CORTEX_A65_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc cortex_a65_cpu_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex-A65. Must follow AAPCS.
+ */
+func cortex_a65_errata_report
+       stp     x8, x30, [sp, #-16]!
+
+       bl      cpu_get_rev_var
+       mov     x8, x0
+
+       /*
+        * Report all errata. The revision-variant information is passed to
+        * checking functions of each errata.
+        */
+       report_errata ERRATA_DSU_936184, cortex_a65, dsu_936184
+
+       ldp     x8, x30, [sp], #16
+       ret
+endfunc cortex_a65_errata_report
+#endif
+
+.section .rodata.cortex_a65_regs, "aS"
+cortex_a65_regs:  /* The ascii list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func cortex_a65_cpu_reg_dump
+       adr     x6, cortex_a65_regs
+       mrs     x8, CORTEX_A65_ECTLR_EL1
+       ret
+endfunc cortex_a65_cpu_reg_dump
+
+declare_cpu_ops cortex_a65, CORTEX_A65_MIDR, \
+       cortex_a65_reset_func, \
+       cortex_a65_cpu_pwr_dwn

diff --git a/plat/arm/board/a5ds/a5ds_pm.c b/plat/arm/board/a5ds/a5ds_pm.c
index 98de77d10dfb02721939821ca9a3148bc4cbca63..cc734b005445e76ab7ac70734d578cab888e2445 100644 (file)
--- a/plat/arm/board/a5ds/a5ds_pm.c
+++ b/plat/arm/board/a5ds/a5ds_pm.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
+#include <assert.h>
 
 #include <lib/psci/psci.h>
 #include <plat/arm/common/plat_arm.h>
@@ -39,6 +40,18 @@ void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state)
        gicv2_cpuif_enable();
 }
 
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
+ * a5ds only has always-on power domain and there is no power control present.
+ ******************************************************************************/
+void a5ds_pwr_domain_off(const psci_power_state_t *target_state)
+{
+       ERROR("CPU_OFF not supported on this platform\n");
+       assert(false);
+       panic();
+}
+
 /*******************************************************************************
  * Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
  * platform layer will take care of registering the handlers with PSCI.
@@ -47,7 +60,8 @@ plat_psci_ops_t a5ds_psci_pm_ops = {
        /* dummy struct */
        .validate_ns_entrypoint = NULL,
        .pwr_domain_on = a5ds_pwr_domain_on,
-       .pwr_domain_on_finish = a5ds_pwr_domain_on_finish
+       .pwr_domain_on_finish = a5ds_pwr_domain_on_finish,
+       .pwr_domain_off = a5ds_pwr_domain_off
 };
 
 int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2bba6bd097cfb74f65f7002751860346d4eae054..c8e2169c32b07b080fb0d93ee455ca2b1dc01b73 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -116,7 +116,8 @@ else
                                        lib/cpus/aarch64/neoverse_e1.S          \
                                        lib/cpus/aarch64/neoverse_zeus.S        \
                                        lib/cpus/aarch64/cortex_hercules.S      \
-                                       lib/cpus/aarch64/cortex_hercules_ae.S
+                                       lib/cpus/aarch64/cortex_hercules_ae.S   \
+                                       lib/cpus/aarch64/cortex_a65.S
        endif
        # AArch64/AArch32 cores
        FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a55.S           \