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(parent: ea53f1c) | patch
riscv: Add exception codes for xcause register
authorBin Meng <bmeng.cn@gmail.com>
Wed, 12 Dec 2018 14:12:37 +0000 (06:12 -0800)
committerAndes <uboot@andestech.com>
Tue, 18 Dec 2018 01:56:27 +0000 (09:56 +0800)
commit3967156464282df161f5e4be40999dae47adf799
tree4a1a5d03f2c44920b250cf9f3b1ad826f3634d8dtree | snapshot
parentea53f1c74272bd7b1d9c8a28df4ac145c72131ddcommit | diff
riscv: Add exception codes for xcause register

This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/encoding.h diff | blob | history
Broadcom-s U-Boot