plat/amlogic/g12a/g12a_common.c

   1 /*
   2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <bl31/interrupt_mgmt.h>
   9 #include <common/bl_common.h>
  10 #include <common/ep_info.h>
  11 #include <lib/mmio.h>
  12 #include <lib/xlat_tables/xlat_tables_v2.h>
  13 #include <platform_def.h>
  14 #include <stdint.h>
  15
  16 /*******************************************************************************
  17  * Platform memory map regions
  18  ******************************************************************************/
  19 #define MAP_NSDRAM0             MAP_REGION_FLAT(AML_NSDRAM0_BASE,               \
  20                                                 AML_NSDRAM0_SIZE,               \
  21                                                 MT_MEMORY | MT_RW | MT_NS)
  22
  23 #define MAP_NS_SHARE_MEM        MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE,          \
  24                                                 AML_NS_SHARE_MEM_SIZE,          \
  25                                                 MT_MEMORY | MT_RW | MT_NS)
  26
  27 #define MAP_SEC_SHARE_MEM       MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE,         \
  28                                                 AML_SEC_SHARE_MEM_SIZE,         \
  29                                                 MT_MEMORY | MT_RW | MT_SECURE)
  30
  31 #define MAP_SEC_DEVICE0         MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE,           \
  32                                                 AML_SEC_DEVICE0_SIZE,           \
  33                                                 MT_DEVICE | MT_RW)
  34
  35 #define MAP_HDCP_RX             MAP_REGION_FLAT(AML_HDCP_RX_BASE,               \
  36                                                 AML_HDCP_RX_SIZE,               \
  37                                                 MT_DEVICE | MT_RW | MT_SECURE)
  38
  39 #define MAP_HDCP_TX             MAP_REGION_FLAT(AML_HDCP_TX_BASE,               \
  40                                                 AML_HDCP_TX_SIZE,               \
  41                                                 MT_DEVICE | MT_RW | MT_SECURE)
  42
  43 #define MAP_GIC_DEVICE          MAP_REGION_FLAT(AML_GIC_DEVICE_BASE,            \
  44                                                 AML_GIC_DEVICE_SIZE,            \
  45                                                 MT_DEVICE | MT_RW | MT_SECURE)
  46
  47 #define MAP_SEC_DEVICE1         MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE,           \
  48                                                 AML_SEC_DEVICE1_SIZE,           \
  49                                                 MT_DEVICE | MT_RW | MT_SECURE)
  50
  51 #define MAP_SEC_DEVICE2         MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE,           \
  52                                                 AML_SEC_DEVICE2_SIZE,           \
  53                                                 MT_DEVICE | MT_RW | MT_SECURE)
  54
  55 #define MAP_TZRAM               MAP_REGION_FLAT(AML_TZRAM_BASE,                 \
  56                                                 AML_TZRAM_SIZE,                 \
  57                                                 MT_DEVICE | MT_RW | MT_SECURE)
  58
  59 static const mmap_region_t g12a_mmap[] = {
  60         MAP_NSDRAM0,
  61         MAP_NS_SHARE_MEM,
  62         MAP_SEC_SHARE_MEM,
  63         MAP_SEC_DEVICE0,
  64         MAP_HDCP_RX,
  65         MAP_HDCP_TX,
  66         MAP_GIC_DEVICE,
  67         MAP_SEC_DEVICE1,
  68         MAP_SEC_DEVICE2,
  69         MAP_TZRAM,
  70         {0}
  71 };
  72
  73 /*******************************************************************************
  74  * Per-image regions
  75  ******************************************************************************/
  76 #define MAP_BL31        MAP_REGION_FLAT(BL31_BASE,                                      \
  77                                         BL31_END - BL31_BASE,                           \
  78                                         MT_MEMORY | MT_RW | MT_SECURE)
  79
  80 #define MAP_BL_CODE     MAP_REGION_FLAT(BL_CODE_BASE,                                   \
  81                                         BL_CODE_END - BL_CODE_BASE,                     \
  82                                         MT_CODE | MT_SECURE)
  83
  84 #define MAP_BL_RO_DATA  MAP_REGION_FLAT(BL_RO_DATA_BASE,                                \
  85                                         BL_RO_DATA_END - BL_RO_DATA_BASE,               \
  86                                         MT_RO_DATA | MT_SECURE)
  87
  88 #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,                           \
  89                                         BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,     \
  90                                         MT_DEVICE | MT_RW | MT_SECURE)
  91
  92 /*******************************************************************************
  93  * Function that sets up the translation tables.
  94  ******************************************************************************/
  95 void aml_setup_page_tables(void)
  96 {
  97 #if IMAGE_BL31
  98         const mmap_region_t g12a_bl_mmap[] = {
  99                 MAP_BL31,
 100                 MAP_BL_CODE,
 101                 MAP_BL_RO_DATA,
 102 #if USE_COHERENT_MEM
 103                 MAP_BL_COHERENT,
 104 #endif
 105                 {0}
 106         };
 107 #endif
 108
 109         mmap_add(g12a_bl_mmap);
 110
 111         mmap_add(g12a_mmap);
 112
 113         init_xlat_tables();
 114 }
 115
 116 /*******************************************************************************
 117  * Function that returns the system counter frequency
 118  ******************************************************************************/
 119 unsigned int plat_get_syscnt_freq2(void)
 120 {
 121         mmio_clrbits_32(AML_SYS_CPU_CFG7, ~0xFDFFFFFF);
 122         mmio_clrbits_32(AML_AO_TIMESTAMP_CNTL, ~0xFFFFFE00);
 123
 124         return AML_OSC24M_CLK_IN_HZ;
 125 }