docs/plat/intel-agilex.rst

   1 Intel Agilex SoCFPGA
   2 ========================
   3
   4 Agilex SoCFPGA is a FPGA with integrated quad-core 64-bit Arm Cortex A53 processor.
   5
   6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
   7 the hardware, then loads bl31 and bl33 (UEFI) into DDR and boots to bl33.
   8
   9 ::
  10
  11     Boot ROM --> Trusted Firmware-A --> UEFI
  12
  13 How to build
  14 ------------
  15
  16 Code Locations
  17 ~~~~~~~~~~~~~~
  18
  19 -  Trusted Firmware-A:
  20    `link <https://github.com/ARM-software/arm-trusted-firmware>`__
  21
  22 -  UEFI (to be updated with new upstreamed UEFI):
  23    `link <https://github.com/altera-opensource/uefi-socfpga>`__
  24
  25 Build Procedure
  26 ~~~~~~~~~~~~~~~
  27
  28 -  Fetch all the above 2 repositories into local host.
  29    Make all the repositories in the same ${BUILD\_PATH}.
  30
  31 -  Prepare the AARCH64 toolchain.
  32
  33 -  Build UEFI using Agilex platform as configuration
  34    This will be updated to use an updated UEFI using the latest EDK2 source
  35
  36 .. code:: bash
  37
  38        make CROSS_COMPILE=aarch64-linux-gnu- device=agx
  39
  40 -  Build atf providing the previously generated UEFI as the BL33 image
  41
  42 .. code:: bash
  43
  44        make CROSS_COMPILE=aarch64-linux-gnu- bl2 fip PLAT=agilex
  45        BL33=PEI.ROM
  46
  47 Install Procedure
  48 ~~~~~~~~~~~~~~~~~
  49
  50 - dd fip.bin to a A2 partition on the MMC drive to be booted in Agilex
  51   board.
  52
  53 - Generate a SOF containing bl2
  54
  55 .. code:: bash
  56
  57         aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
  58         quartus_cpf --bootloader bl2.hex <quartus_generated_sof> <output_sof_with_bl2>
  59
  60 - Configure SOF to board
  61
  62 .. code:: bash
  63
  64         nios2-configure-sof <output_sof_with_bl2>
  65
  66 Boot trace
  67 ----------
  68
  69 ::
  70         INFO:    DDR: DRAM calibration success.
  71         INFO:    ECC is disabled.
  72         NOTICE:  BL2: v2.1(debug)
  73         NOTICE:  BL2: Built
  74         INFO:    BL2: Doing platform setup
  75         NOTICE:  BL2: Booting BL31
  76         INFO:    Entry point address = 0xffe1c000
  77         INFO:    SPSR = 0x3cd
  78         NOTICE:  BL31: v2.1(debug)
  79         NOTICE:  BL31: Built
  80         INFO:    ARM GICv2 driver initialized
  81         INFO:    BL31: Initializing runtime services
  82         WARNING: BL31: cortex_a53
  83         INFO:    BL31: Preparing for EL3 exit to normal world
  84         INFO:    Entry point address = 0x50000
  85         INFO:    SPSR = 0x3c9