target/linux/bcm27xx/patches-6.1/950-0873-dt-bindings-clock-Add-bindings-for-Raspberry-Pi-RP1.patch

   1 From 00ff2819eb852b54fe22e7181646e40d560576dc Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Fri, 28 Oct 2022 14:12:18 +0100
   4 Subject: [PATCH] dt-bindings: clock: Add bindings for Raspberry Pi RP1
   5
   6 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
   7 ---
   8  include/dt-bindings/clock/rp1.h | 51 +++++++++++++++++++++++++++++++++
   9  1 file changed, 51 insertions(+)
  10  create mode 100644 include/dt-bindings/clock/rp1.h
  11
  12 --- /dev/null
  13 +++ b/include/dt-bindings/clock/rp1.h
  14 @@ -0,0 +1,51 @@
  15 +/* SPDX-License-Identifier: GPL-2.0 */
  16 +/*
  17 + * Copyright (C) 2021 Raspberry Pi Ltd.
  18 + */
  19 +
  20 +#define RP1_PLL_SYS_CORE               0
  21 +#define RP1_PLL_AUDIO_CORE             1
  22 +#define RP1_PLL_VIDEO_CORE             2
  23 +
  24 +#define RP1_PLL_SYS                    3
  25 +#define RP1_PLL_AUDIO                  4
  26 +#define RP1_PLL_VIDEO                  5
  27 +
  28 +#define RP1_PLL_SYS_PRI_PH             6
  29 +#define RP1_PLL_SYS_SEC_PH             7
  30 +
  31 +#define RP1_PLL_SYS_SEC                        8
  32 +#define RP1_PLL_AUDIO_SEC              9
  33 +#define RP1_PLL_VIDEO_SEC              10
  34 +
  35 +#define RP1_CLK_SYS                    11
  36 +#define RP1_CLK_SLOW_SYS               12
  37 +#define RP1_CLK_DMA                    13
  38 +#define RP1_CLK_UART                   14
  39 +#define RP1_CLK_ETH                    15
  40 +#define RP1_CLK_PWM0                   16
  41 +#define RP1_CLK_PWM1                   17
  42 +#define RP1_CLK_AUDIO_IN               18
  43 +#define RP1_CLK_AUDIO_OUT              19
  44 +#define RP1_CLK_I2S                    20
  45 +#define RP1_CLK_MIPI0_CFG              21
  46 +#define RP1_CLK_MIPI1_CFG              22
  47 +#define RP1_CLK_PCIE_AUX               23
  48 +#define RP1_CLK_USBH0_MICROFRAME       24
  49 +#define RP1_CLK_USBH1_MICROFRAME       25
  50 +#define RP1_CLK_USBH0_SUSPEND          26
  51 +#define RP1_CLK_USBH1_SUSPEND          27
  52 +#define RP1_CLK_ETH_TSU                        28
  53 +#define RP1_CLK_ADC                    29
  54 +#define RP1_CLK_SDIO_TIMER             30
  55 +#define RP1_CLK_SDIO_ALT_SRC           31
  56 +#define RP1_CLK_GP0                    32
  57 +#define RP1_CLK_GP1                    33
  58 +#define RP1_CLK_GP2                    34
  59 +#define RP1_CLK_GP3                    35
  60 +#define RP1_CLK_GP4                    36
  61 +#define RP1_CLK_GP5                    37
  62 +#define RP1_CLK_VEC                    38
  63 +#define RP1_CLK_DPI                    39
  64 +#define RP1_CLK_MIPI0_DPI              40
  65 +#define RP1_CLK_MIPI1_DPI              41