target/linux/bcm27xx/patches-6.1/950-0975-drm-vc4-Add-additional-warn_on.patch

   1 From bb05ccd66342643b1cd9a0a48cec3ebdc3eed511 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Tue, 21 Feb 2023 14:38:32 +0100
   4 Subject: [PATCH] drm/vc4: Add additional warn_on
   5
   6 Some code path in vc4 are conditional to a generation and cannot be
   7 executed on others. Let's put a WARN_ON if that ever happens.
   8
   9 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  10 ---
  11  drivers/gpu/drm/vc4/vc4_hvs.c   | 32 ++++++++++++++++++++++++++++++--
  12  drivers/gpu/drm/vc4/vc4_kms.c   |  6 ++++++
  13  drivers/gpu/drm/vc4/vc4_plane.c | 19 +++++++++++++++++++
  14  3 files changed, 55 insertions(+), 2 deletions(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  18 @@ -417,12 +417,15 @@ static int vc4_hvs_upload_linear_kernel(
  19  static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
  20                              struct vc4_crtc *vc4_crtc)
  21  {
  22 -       struct drm_device *drm = &hvs->vc4->base;
  23 +       struct vc4_dev *vc4 = hvs->vc4;
  24 +       struct drm_device *drm = &vc4->base;
  25         struct drm_crtc *crtc = &vc4_crtc->base;
  26         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
  27         int idx;
  28         u32 i;
  29
  30 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
  31 +
  32         if (!drm_dev_enter(drm, &idx))
  33                 return;
  34
  35 @@ -758,6 +761,8 @@ u8 vc4_hvs_get_fifo_frame_count(struct v
  36         u8 field = 0;
  37         int idx;
  38
  39 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
  40 +
  41         if (!drm_dev_enter(drm, &idx))
  42                 return 0;
  43
  44 @@ -791,6 +796,8 @@ int vc4_hvs_get_fifo_from_output(struct
  45         u32 reg;
  46         int ret;
  47
  48 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
  49 +
  50         switch (vc4->gen) {
  51         case VC4_GEN_4:
  52                 return output;
  53 @@ -880,6 +887,8 @@ static int vc4_hvs_init_channel(struct v
  54         u32 dispctrl;
  55         int idx;
  56
  57 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
  58 +
  59         if (!drm_dev_enter(drm, &idx))
  60                 return -ENODEV;
  61
  62 @@ -947,6 +956,8 @@ static int vc6_hvs_init_channel(struct v
  63         u32 disp_ctrl1;
  64         int idx;
  65
  66 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
  67 +
  68         if (!drm_dev_enter(drm, &idx))
  69                 return -ENODEV;
  70
  71 @@ -972,9 +983,12 @@ static int vc6_hvs_init_channel(struct v
  72
  73  static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
  74  {
  75 -       struct drm_device *drm = &hvs->vc4->base;
  76 +       struct vc4_dev *vc4 = hvs->vc4;
  77 +       struct drm_device *drm = &vc4->base;
  78         int idx;
  79
  80 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
  81 +
  82         if (!drm_dev_enter(drm, &idx))
  83                 return;
  84
  85 @@ -1007,6 +1021,8 @@ static void __vc6_hvs_stop_channel(struc
  86         struct drm_device *drm = &vc4->base;
  87         int idx;
  88
  89 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
  90 +
  91         if (!drm_dev_enter(drm, &idx))
  92                 return;
  93
  94 @@ -1234,6 +1250,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
  95         bool found = false;
  96         int idx;
  97
  98 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
  99 +
 100         if (!drm_dev_enter(dev, &idx)) {
 101                 vc4_crtc_send_vblank(crtc);
 102                 return;
 103 @@ -1324,6 +1342,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
 104         if (crtc->state->color_mgmt_changed) {
 105                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
 106
 107 +               WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
 108 +
 109                 if (crtc->state->gamma_lut) {
 110                         if (vc4->gen == VC4_GEN_4) {
 111                                 vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
 112 @@ -1363,6 +1383,8 @@ void vc4_hvs_mask_underrun(struct vc4_hv
 113         u32 dispctrl;
 114         int idx;
 115
 116 +       WARN_ON(vc4->gen > VC4_GEN_5);
 117 +
 118         if (!drm_dev_enter(drm, &idx))
 119                 return;
 120
 121 @@ -1383,6 +1405,8 @@ void vc4_hvs_unmask_underrun(struct vc4_
 122         u32 dispctrl;
 123         int idx;
 124
 125 +       WARN_ON(vc4->gen > VC4_GEN_5);
 126 +
 127         if (!drm_dev_enter(drm, &idx))
 128                 return;
 129
 130 @@ -1417,6 +1441,8 @@ static irqreturn_t vc4_hvs_irq_handler(i
 131         u32 status;
 132         u32 dspeislur;
 133
 134 +       WARN_ON(vc4->gen > VC4_GEN_5);
 135 +
 136         /*
 137          * NOTE: We don't need to protect the register access using
 138          * drm_dev_enter() there because the interrupt handler lifetime
 139 @@ -1466,6 +1492,8 @@ static irqreturn_t vc6_hvs_eof_irq_handl
 140         struct vc4_hvs *hvs = vc4->hvs;
 141         unsigned int i;
 142
 143 +       WARN_ON(vc4->gen < VC4_GEN_6);
 144 +
 145         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 146                 if (!hvs->eof_irq[i].enabled)
 147                         continue;
 148 --- a/drivers/gpu/drm/vc4/vc4_kms.c
 149 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
 150 @@ -147,6 +147,8 @@ vc4_ctm_commit(struct vc4_dev *vc4, stru
 151         if (vc4->firmware_kms)
 152                 return;
 153
 154 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
 155 +
 156         if (ctm_state->fifo) {
 157                 HVS_WRITE(SCALER_OLEDCOEF2,
 158                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 159 @@ -222,6 +224,8 @@ static void vc4_hvs_pv_muxing_commit(str
 160         struct drm_crtc *crtc;
 161         unsigned int i;
 162
 163 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
 164 +
 165         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 166                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 167                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 168 @@ -265,6 +269,8 @@ static void vc5_hvs_pv_muxing_commit(str
 169         unsigned int i;
 170         u32 reg;
 171
 172 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_5);
 173 +
 174         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 175                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 176                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 177 --- a/drivers/gpu/drm/vc4/vc4_plane.c
 178 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
 179 @@ -555,8 +555,11 @@ static int vc4_plane_setup_clipping_and_
 180
 181  static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 182  {
 183 +       struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
 184         u32 scale, recip;
 185
 186 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
 187 +
 188         scale = src / dst;
 189
 190         /* The specs note that while the reciprocal would be defined
 191 @@ -581,10 +584,13 @@ static void vc4_write_tpz(struct vc4_pla
 192
 193  static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel, int chroma_offset)
 194  {
 195 +       struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
 196         u32 scale = src / dst;
 197         s32 offset, offset2;
 198         s32 phase;
 199
 200 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
 201 +
 202         /* Start the phase at 1/2 pixel from the 1st pixel at src_x.
 203            1/4 pixel for YUV, plus the offset for chroma siting */
 204         if (channel) {
 205 @@ -801,8 +807,11 @@ static size_t vc6_upm_size(const struct
 206  static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 207                                          int channel)
 208  {
 209 +       struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
 210         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 211
 212 +       WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
 213 +
 214         /* Ch0 H-PPF Word 0: Scaling Parameters */
 215         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 216                 vc4_write_ppf(vc4_state,
 217 @@ -1040,6 +1049,11 @@ static const u32 colorspace_coeffs[2][DR
 218
 219  static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
 220  {
 221 +       struct drm_device *dev = state->state->dev;
 222 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 223 +
 224 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
 225 +
 226         if (!state->fb->format->has_alpha)
 227                 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
 228                                      SCALER_POS2_ALPHA_MODE);
 229 @@ -1061,6 +1075,11 @@ static u32 vc4_hvs4_get_alpha_blend_mode
 230
 231  static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
 232  {
 233 +       struct drm_device *dev = state->state->dev;
 234 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 235 +
 236 +       WARN_ON_ONCE(vc4->gen != VC4_GEN_5 && vc4->gen != VC4_GEN_6);
 237 +
 238         if (!state->fb->format->has_alpha)
 239                 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
 240                                      SCALER5_CTL2_ALPHA_MODE);