1 From 8559b2db6aecbee62cf9e02c17349379d72edcfb Mon Sep 17 00:00:00 2001
2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
3 Date: Tue, 14 Mar 2023 21:24:35 +0800
4 Subject: [PATCH 104/122] dt-bindings: watchdog: Add watchdog for StarFive
7 Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
8 And Use JH7100 as first StarFive SoC with watchdog.
10 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
11 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 Reviewed-by: Guenter Roeck <linux@roeck-us.net>
14 .../watchdog/starfive,jh7100-wdt.yaml | 71 +++++++++++++++++++
15 1 file changed, 71 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml
19 +++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml
21 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24 +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
25 +$schema: http://devicetree.org/meta-schemas/core.yaml#
27 +title: StarFive Watchdog for JH7100 and JH7110 SoC
30 + - Xingyu Wu <xingyu.wu@starfivetech.com>
31 + - Samin Guo <samin.guo@starfivetech.com>
34 + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
35 + has only one timeout phase and reboots. And JH7110 watchdog has two
36 + timeout phases. At the first phase, the signal of watchdog interrupt
37 + output(WDOGINT) will rise when counter is 0. The counter will reload
38 + the timeout value. And then, if counter decreases to 0 again and WDOGINT
39 + isn't cleared, the watchdog will reset the system unless the watchdog
43 + - $ref: watchdog.yaml#
48 + - starfive,jh7100-wdt
49 + - starfive,jh7110-wdt
59 + - description: APB clock
60 + - description: Core clock
69 + - description: APB reset
70 + - description: Core reset
79 +unevaluatedProperties: false
84 + compatible = "starfive,jh7100-wdt";
85 + reg = <0x12480000 0x10000>;
86 + clocks = <&clk 171>,
88 + clock-names = "apb", "core";