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starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0006-clk-starfive-Rename-jh7100-to-jh71x0-for-the-common-.patch
1 From 674fa25b207e4bef6c27af2acfbca3a0d765a45b Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Sat, 1 Apr 2023 19:19:18 +0800
4 Subject: [PATCH 006/122] clk: starfive: Rename "jh7100" to "jh71x0" for the
5 common code
6
7 Rename some variables from "jh7100" or "JH7100" to "jh71x0"
8 or "JH71X0".
9
10 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
11 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
12 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
14 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
15 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
16 ---
17 .../clk/starfive/clk-starfive-jh7100-audio.c | 72 ++--
18 drivers/clk/starfive/clk-starfive-jh7100.c | 389 +++++++++---------
19 drivers/clk/starfive/clk-starfive-jh71x0.c | 282 ++++++-------
20 drivers/clk/starfive/clk-starfive-jh71x0.h | 81 ++--
21 4 files changed, 418 insertions(+), 406 deletions(-)
22
23 --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
24 +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
25 @@ -28,66 +28,66 @@
26 #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
27 #define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
28
29 -static const struct jh7100_clk_data jh7100_audclk_data[] = {
30 - JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
31 +static const struct jh71x0_clk_data jh7100_audclk_data[] = {
32 + JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
33 JH7100_AUDCLK_AUDIO_SRC,
34 JH7100_AUDCLK_AUDIO_12288),
35 - JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
36 + JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
37 JH7100_AUDCLK_AUDIO_SRC,
38 JH7100_AUDCLK_AUDIO_12288),
39 - JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
40 - JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
41 + JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
42 + JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
43 JH7100_AUDCLK_ADC_MCLK,
44 JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
45 - JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
46 - JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
47 + JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
48 + JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
49 JH7100_AUDCLK_I2SADC_BCLK_N,
50 JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
51 JH7100_AUDCLK_I2SADC_BCLK),
52 - JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
53 - JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
54 + JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
55 + JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
56 JH7100_AUDCLK_AUDIO_SRC,
57 JH7100_AUDCLK_AUDIO_12288),
58 - JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
59 - JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
60 + JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
61 + JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
62 JH7100_AUDCLK_AUDIO_SRC,
63 JH7100_AUDCLK_AUDIO_12288),
64 - JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
65 - JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
66 - JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
67 + JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
68 + JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
69 + JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
70 JH7100_AUDCLK_AUDIO_SRC,
71 JH7100_AUDCLK_AUDIO_12288),
72 - JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
73 - JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
74 + JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
75 + JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
76 JH7100_AUDCLK_DAC_MCLK,
77 JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
78 - JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
79 - JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
80 + JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
81 + JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
82 JH7100_AUDCLK_I2S1_MCLK,
83 JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
84 - JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
85 - JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
86 + JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
87 + JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
88 JH7100_AUDCLK_I2S1_MCLK,
89 JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
90 - JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
91 - JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
92 + JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
93 + JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
94 JH7100_AUDCLK_I2S1_BCLK_N,
95 JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
96 - JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
97 - JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
98 - JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
99 - JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
100 - JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
101 - JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
102 - JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
103 - JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
104 + JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
105 + JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
106 + JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
107 + JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
108 + JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
109 + JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
110 + JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
111 + JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
112 JH7100_AUDCLK_VAD_INTMEM,
113 JH7100_AUDCLK_AUDIO_12288),
114 };
115
116 static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
117 {
118 - struct jh7100_clk_priv *priv = data;
119 + struct jh71x0_clk_priv *priv = data;
120 unsigned int idx = clkspec->args[0];
121
122 if (idx < JH7100_AUDCLK_END)
123 @@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(
124
125 static int jh7100_audclk_probe(struct platform_device *pdev)
126 {
127 - struct jh7100_clk_priv *priv;
128 + struct jh71x0_clk_priv *priv;
129 unsigned int idx;
130 int ret;
131
132 @@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct pl
133 struct clk_parent_data parents[4] = {};
134 struct clk_init_data init = {
135 .name = jh7100_audclk_data[idx].name,
136 - .ops = starfive_jh7100_clk_ops(max),
137 + .ops = starfive_jh71x0_clk_ops(max),
138 .parent_data = parents,
139 - .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
140 + .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
141 .flags = jh7100_audclk_data[idx].flags,
142 };
143 - struct jh7100_clk *clk = &priv->reg[idx];
144 + struct jh71x0_clk *clk = &priv->reg[idx];
145 unsigned int i;
146
147 for (i = 0; i < init.num_parents; i++) {
148 @@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct pl
149
150 clk->hw.init = &init;
151 clk->idx = idx;
152 - clk->max_div = max & JH7100_CLK_DIV_MASK;
153 + clk->max_div = max & JH71X0_CLK_DIV_MASK;
154
155 ret = devm_clk_hw_register(priv->dev, &clk->hw);
156 if (ret)
157 --- a/drivers/clk/starfive/clk-starfive-jh7100.c
158 +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
159 @@ -23,250 +23,253 @@
160 #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
161 #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
162
163 -static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
164 - JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
165 +static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
166 + JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
167 JH7100_CLK_OSC_SYS,
168 JH7100_CLK_PLL0_OUT,
169 JH7100_CLK_PLL1_OUT,
170 JH7100_CLK_PLL2_OUT),
171 - JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
172 + JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
173 JH7100_CLK_OSC_SYS,
174 JH7100_CLK_PLL1_OUT,
175 JH7100_CLK_PLL2_OUT),
176 - JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
177 + JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
178 JH7100_CLK_OSC_SYS,
179 JH7100_CLK_PLL0_OUT,
180 JH7100_CLK_PLL1_OUT,
181 JH7100_CLK_PLL2_OUT),
182 - JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
183 + JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
184 JH7100_CLK_OSC_SYS,
185 JH7100_CLK_PLL0_OUT,
186 JH7100_CLK_PLL2_OUT),
187 - JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
188 + JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
189 JH7100_CLK_OSC_SYS,
190 JH7100_CLK_PLL0_OUT),
191 - JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
192 + JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
193 JH7100_CLK_OSC_SYS,
194 JH7100_CLK_PLL2_OUT),
195 - JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
196 + JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
197 JH7100_CLK_OSC_SYS,
198 JH7100_CLK_PLL1_OUT,
199 JH7100_CLK_PLL2_OUT),
200 - JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
201 + JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
202 JH7100_CLK_OSC_AUD,
203 JH7100_CLK_PLL0_OUT,
204 JH7100_CLK_PLL2_OUT),
205 - JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
206 - JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
207 + JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
208 + JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
209 JH7100_CLK_OSC_SYS,
210 JH7100_CLK_PLL1_OUT,
211 JH7100_CLK_PLL2_OUT),
212 - JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
213 + JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
214 JH7100_CLK_OSC_SYS,
215 JH7100_CLK_PLL0_OUT,
216 JH7100_CLK_PLL1_OUT),
217 - JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
218 + JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
219 JH7100_CLK_OSC_AUD,
220 JH7100_CLK_PLL0_OUT,
221 JH7100_CLK_PLL2_OUT),
222 - JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
223 - JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
224 - JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
225 - JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
226 - JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
227 - JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
228 - JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
229 - JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
230 + JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
231 + JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
232 + JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
233 + JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
234 + JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
235 + JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
236 + JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
237 + JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
238 JH7100_CLK_OSC_SYS,
239 JH7100_CLK_OSC_AUD),
240 - JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
241 - JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
242 - JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
243 - JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
244 - JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
245 - JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
246 - JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
247 - JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
248 - JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
249 - JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
250 - JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
251 - JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
252 - JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
253 - JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
254 - JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
255 - JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
256 - JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
257 - JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
258 - JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
259 - JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
260 - JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
261 - JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
262 - JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
263 - JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
264 - JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
265 - JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
266 - JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
267 - JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
268 - JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
269 - JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
270 - JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
271 - JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
272 - JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
273 - JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
274 - JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
275 - JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
276 - JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
277 - JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
278 - JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
279 - JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
280 - JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
281 - JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
282 - JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
283 - JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
284 - JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
285 - JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
286 - JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
287 + JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
288 + JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
289 + JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
290 + JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
291 + JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
292 + JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
293 + JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
294 + JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
295 + JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
296 + JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
297 + JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
298 + JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
299 + JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
300 + JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
301 + JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
302 + JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
303 + JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
304 + JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
305 + JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
306 + JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
307 + JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
308 + JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
309 + JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
310 + JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
311 + JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
312 + JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
313 + JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
314 + JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
315 + JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
316 + JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
317 + JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
318 + JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
319 + JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
320 + JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
321 + JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
322 + JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
323 + JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
324 + JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
325 + JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
326 + JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
327 + JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
328 + JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
329 + JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
330 + JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
331 + JH7100_CLK_DDRPLL_DIV2),
332 + JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
333 + JH7100_CLK_DDRPLL_DIV4),
334 + JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
335 + JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
336 JH7100_CLK_DDROSC_DIV2,
337 JH7100_CLK_DDRPLL_DIV2,
338 JH7100_CLK_DDRPLL_DIV4,
339 JH7100_CLK_DDRPLL_DIV8),
340 - JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
341 + JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
342 JH7100_CLK_DDROSC_DIV2,
343 JH7100_CLK_DDRPLL_DIV2,
344 JH7100_CLK_DDRPLL_DIV4,
345 JH7100_CLK_DDRPLL_DIV8),
346 - JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
347 - JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
348 - JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
349 - JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
350 - JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
351 - JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
352 + JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
353 + JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
354 + JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
355 + JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
356 + JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
357 + JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
358 JH7100_CLK_CPU_AXI,
359 JH7100_CLK_NNEBUS_SRC1),
360 - JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
361 - JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
362 - JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
363 - JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
364 - JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
365 - JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
366 - JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
367 - JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
368 - JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
369 - JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
370 - JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
371 - JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
372 - JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
373 - JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
374 - JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
375 - JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
376 - JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
377 - JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
378 - JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
379 - JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
380 - JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
381 + JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
382 + JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
383 + JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
384 + JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
385 + JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
386 + JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
387 + JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
388 + JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
389 + JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
390 + JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
391 + JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
392 + JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
393 + JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
394 + JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
395 + JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
396 + JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
397 + JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
398 + JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
399 + JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
400 + JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
401 + JH7100_CLK_USBPHY_ROOTDIV),
402 + JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
403 JH7100_CLK_OSC_SYS,
404 JH7100_CLK_USBPHY_PLLDIV25M),
405 - JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
406 - JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
407 - JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
408 - JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
409 - JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
410 - JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
411 - JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
412 - JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
413 - JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
414 - JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
415 - JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
416 - JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
417 - JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
418 - JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
419 - JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
420 - JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
421 - JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
422 - JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
423 - JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
424 - JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
425 - JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
426 - JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
427 - JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
428 - JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
429 - JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
430 - JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
431 - JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
432 - JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
433 - JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
434 - JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
435 - JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
436 - JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
437 + JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
438 + JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
439 + JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
440 + JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
441 + JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
442 + JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
443 + JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
444 + JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
445 + JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
446 + JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
447 + JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
448 + JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
449 + JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
450 + JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
451 + JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
452 + JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
453 + JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
454 + JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
455 + JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
456 + JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
457 + JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
458 + JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
459 + JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
460 + JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
461 + JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
462 + JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
463 + JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
464 + JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
465 + JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
466 + JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
467 + JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
468 + JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
469 JH7100_CLK_GMAC_GTX,
470 JH7100_CLK_GMAC_TX_INV,
471 JH7100_CLK_GMAC_RMII_TX),
472 - JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
473 - JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
474 + JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
475 + JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
476 JH7100_CLK_GMAC_GR_MII_RX,
477 JH7100_CLK_GMAC_RMII_RX),
478 - JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
479 - JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
480 - JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
481 - JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
482 - JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
483 - JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
484 - JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
485 - JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
486 - JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
487 - JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
488 - JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
489 - JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
490 - JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
491 - JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
492 - JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
493 - JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
494 - JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
495 - JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
496 - JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
497 - JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
498 - JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
499 - JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
500 - JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
501 - JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
502 - JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
503 - JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
504 - JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
505 - JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
506 - JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
507 - JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
508 - JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
509 - JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
510 - JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
511 - JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
512 - JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
513 - JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
514 - JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
515 - JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
516 - JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
517 - JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
518 - JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
519 - JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
520 - JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
521 - JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
522 - JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
523 - JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
524 - JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
525 - JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
526 - JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
527 - JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
528 - JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
529 - JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
530 - JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
531 - JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
532 - JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
533 - JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
534 - JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
535 + JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
536 + JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
537 + JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
538 + JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
539 + JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
540 + JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
541 + JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
542 + JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
543 + JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
544 + JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
545 + JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
546 + JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
547 + JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
548 + JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
549 + JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
550 + JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
551 + JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
552 + JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
553 + JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
554 + JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
555 + JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
556 + JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
557 + JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
558 + JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
559 + JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
560 + JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
561 + JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
562 + JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
563 + JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
564 + JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
565 + JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
566 + JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
567 + JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
568 + JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
569 + JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
570 + JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
571 + JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
572 + JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
573 + JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
574 + JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
575 + JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
576 + JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
577 + JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
578 + JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
579 + JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
580 + JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
581 + JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
582 + JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
583 + JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
584 + JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
585 + JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
586 + JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
587 + JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
588 + JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
589 + JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
590 + JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
591 + JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
592 };
593
594 static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
595 {
596 - struct jh7100_clk_priv *priv = data;
597 + struct jh71x0_clk_priv *priv = data;
598 unsigned int idx = clkspec->args[0];
599
600 if (idx < JH7100_CLK_PLL0_OUT)
601 @@ -280,7 +283,7 @@ static struct clk_hw *jh7100_clk_get(str
602
603 static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
604 {
605 - struct jh7100_clk_priv *priv;
606 + struct jh71x0_clk_priv *priv;
607 unsigned int idx;
608 int ret;
609
610 @@ -314,12 +317,12 @@ static int __init clk_starfive_jh7100_pr
611 struct clk_parent_data parents[4] = {};
612 struct clk_init_data init = {
613 .name = jh7100_clk_data[idx].name,
614 - .ops = starfive_jh7100_clk_ops(max),
615 + .ops = starfive_jh71x0_clk_ops(max),
616 .parent_data = parents,
617 - .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
618 + .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
619 .flags = jh7100_clk_data[idx].flags,
620 };
621 - struct jh7100_clk *clk = &priv->reg[idx];
622 + struct jh71x0_clk *clk = &priv->reg[idx];
623 unsigned int i;
624
625 for (i = 0; i < init.num_parents; i++) {
626 @@ -341,7 +344,7 @@ static int __init clk_starfive_jh7100_pr
627
628 clk->hw.init = &init;
629 clk->idx = idx;
630 - clk->max_div = max & JH7100_CLK_DIV_MASK;
631 + clk->max_div = max & JH71X0_CLK_DIV_MASK;
632
633 ret = devm_clk_hw_register(priv->dev, &clk->hw);
634 if (ret)
635 --- a/drivers/clk/starfive/clk-starfive-jh71x0.c
636 +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
637 @@ -1,6 +1,6 @@
638 // SPDX-License-Identifier: GPL-2.0
639 /*
640 - * StarFive JH7100 Clock Generator Driver
641 + * StarFive JH71X0 Clock Generator Driver
642 *
643 * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
644 */
645 @@ -12,27 +12,27 @@
646
647 #include "clk-starfive-jh71x0.h"
648
649 -static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
650 +static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
651 {
652 - return container_of(hw, struct jh7100_clk, hw);
653 + return container_of(hw, struct jh71x0_clk, hw);
654 }
655
656 -static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
657 +static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
658 {
659 - return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
660 + return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
661 }
662
663 -static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
664 +static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
665 {
666 - struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
667 + struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
668 void __iomem *reg = priv->base + 4 * clk->idx;
669
670 return readl_relaxed(reg);
671 }
672
673 -static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
674 +static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
675 {
676 - struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
677 + struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
678 void __iomem *reg = priv->base + 4 * clk->idx;
679 unsigned long flags;
680
681 @@ -42,41 +42,41 @@ static void jh7100_clk_reg_rmw(struct jh
682 spin_unlock_irqrestore(&priv->rmw_lock, flags);
683 }
684
685 -static int jh7100_clk_enable(struct clk_hw *hw)
686 +static int jh71x0_clk_enable(struct clk_hw *hw)
687 {
688 - struct jh7100_clk *clk = jh7100_clk_from(hw);
689 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
690
691 - jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
692 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
693 return 0;
694 }
695
696 -static void jh7100_clk_disable(struct clk_hw *hw)
697 +static void jh71x0_clk_disable(struct clk_hw *hw)
698 {
699 - struct jh7100_clk *clk = jh7100_clk_from(hw);
700 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
701
702 - jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
703 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
704 }
705
706 -static int jh7100_clk_is_enabled(struct clk_hw *hw)
707 +static int jh71x0_clk_is_enabled(struct clk_hw *hw)
708 {
709 - struct jh7100_clk *clk = jh7100_clk_from(hw);
710 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
711
712 - return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
713 + return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
714 }
715
716 -static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
717 +static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
718 unsigned long parent_rate)
719 {
720 - struct jh7100_clk *clk = jh7100_clk_from(hw);
721 - u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
722 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
723 + u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
724
725 return div ? parent_rate / div : 0;
726 }
727
728 -static int jh7100_clk_determine_rate(struct clk_hw *hw,
729 +static int jh71x0_clk_determine_rate(struct clk_hw *hw,
730 struct clk_rate_request *req)
731 {
732 - struct jh7100_clk *clk = jh7100_clk_from(hw);
733 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
734 unsigned long parent = req->best_parent_rate;
735 unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
736 unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
737 @@ -102,232 +102,232 @@ static int jh7100_clk_determine_rate(str
738 return 0;
739 }
740
741 -static int jh7100_clk_set_rate(struct clk_hw *hw,
742 +static int jh71x0_clk_set_rate(struct clk_hw *hw,
743 unsigned long rate,
744 unsigned long parent_rate)
745 {
746 - struct jh7100_clk *clk = jh7100_clk_from(hw);
747 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
748 unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
749 1UL, (unsigned long)clk->max_div);
750
751 - jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
752 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
753 return 0;
754 }
755
756 -static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
757 +static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
758 unsigned long parent_rate)
759 {
760 - struct jh7100_clk *clk = jh7100_clk_from(hw);
761 - u32 reg = jh7100_clk_reg_get(clk);
762 - unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
763 - ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
764 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
765 + u32 reg = jh71x0_clk_reg_get(clk);
766 + unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
767 + ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
768
769 - return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
770 + return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
771 }
772
773 -static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
774 +static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
775 struct clk_rate_request *req)
776 {
777 unsigned long parent100 = 100 * req->best_parent_rate;
778 unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
779 unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
780 - JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
781 + JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
782 unsigned long result = parent100 / div100;
783
784 - /* clamp the result as in jh7100_clk_determine_rate() above */
785 - if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
786 + /* clamp the result as in jh71x0_clk_determine_rate() above */
787 + if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
788 result = parent100 / (div100 + 1);
789 - if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
790 + if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
791 result = parent100 / (div100 - 1);
792
793 req->rate = result;
794 return 0;
795 }
796
797 -static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
798 +static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
799 unsigned long rate,
800 unsigned long parent_rate)
801 {
802 - struct jh7100_clk *clk = jh7100_clk_from(hw);
803 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
804 unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
805 - JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
806 - u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
807 + JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
808 + u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
809
810 - jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
811 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
812 return 0;
813 }
814
815 -static u8 jh7100_clk_get_parent(struct clk_hw *hw)
816 +static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
817 {
818 - struct jh7100_clk *clk = jh7100_clk_from(hw);
819 - u32 value = jh7100_clk_reg_get(clk);
820 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
821 + u32 value = jh71x0_clk_reg_get(clk);
822
823 - return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
824 + return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
825 }
826
827 -static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
828 +static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
829 {
830 - struct jh7100_clk *clk = jh7100_clk_from(hw);
831 - u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
832 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
833 + u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
834
835 - jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
836 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
837 return 0;
838 }
839
840 -static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
841 +static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
842 struct clk_rate_request *req)
843 {
844 return clk_mux_determine_rate_flags(hw, req, 0);
845 }
846
847 -static int jh7100_clk_get_phase(struct clk_hw *hw)
848 +static int jh71x0_clk_get_phase(struct clk_hw *hw)
849 {
850 - struct jh7100_clk *clk = jh7100_clk_from(hw);
851 - u32 value = jh7100_clk_reg_get(clk);
852 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
853 + u32 value = jh71x0_clk_reg_get(clk);
854
855 - return (value & JH7100_CLK_INVERT) ? 180 : 0;
856 + return (value & JH71X0_CLK_INVERT) ? 180 : 0;
857 }
858
859 -static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
860 +static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
861 {
862 - struct jh7100_clk *clk = jh7100_clk_from(hw);
863 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
864 u32 value;
865
866 if (degrees == 0)
867 value = 0;
868 else if (degrees == 180)
869 - value = JH7100_CLK_INVERT;
870 + value = JH71X0_CLK_INVERT;
871 else
872 return -EINVAL;
873
874 - jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
875 + jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
876 return 0;
877 }
878
879 #ifdef CONFIG_DEBUG_FS
880 -static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
881 +static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
882 {
883 - static const struct debugfs_reg32 jh7100_clk_reg = {
884 + static const struct debugfs_reg32 jh71x0_clk_reg = {
885 .name = "CTRL",
886 .offset = 0,
887 };
888 - struct jh7100_clk *clk = jh7100_clk_from(hw);
889 - struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
890 + struct jh71x0_clk *clk = jh71x0_clk_from(hw);
891 + struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
892 struct debugfs_regset32 *regset;
893
894 regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
895 if (!regset)
896 return;
897
898 - regset->regs = &jh7100_clk_reg;
899 + regset->regs = &jh71x0_clk_reg;
900 regset->nregs = 1;
901 regset->base = priv->base + 4 * clk->idx;
902
903 debugfs_create_regset32("registers", 0400, dentry, regset);
904 }
905 #else
906 -#define jh7100_clk_debug_init NULL
907 +#define jh71x0_clk_debug_init NULL
908 #endif
909
910 -static const struct clk_ops jh7100_clk_gate_ops = {
911 - .enable = jh7100_clk_enable,
912 - .disable = jh7100_clk_disable,
913 - .is_enabled = jh7100_clk_is_enabled,
914 - .debug_init = jh7100_clk_debug_init,
915 +static const struct clk_ops jh71x0_clk_gate_ops = {
916 + .enable = jh71x0_clk_enable,
917 + .disable = jh71x0_clk_disable,
918 + .is_enabled = jh71x0_clk_is_enabled,
919 + .debug_init = jh71x0_clk_debug_init,
920 };
921
922 -static const struct clk_ops jh7100_clk_div_ops = {
923 - .recalc_rate = jh7100_clk_recalc_rate,
924 - .determine_rate = jh7100_clk_determine_rate,
925 - .set_rate = jh7100_clk_set_rate,
926 - .debug_init = jh7100_clk_debug_init,
927 +static const struct clk_ops jh71x0_clk_div_ops = {
928 + .recalc_rate = jh71x0_clk_recalc_rate,
929 + .determine_rate = jh71x0_clk_determine_rate,
930 + .set_rate = jh71x0_clk_set_rate,
931 + .debug_init = jh71x0_clk_debug_init,
932 };
933
934 -static const struct clk_ops jh7100_clk_fdiv_ops = {
935 - .recalc_rate = jh7100_clk_frac_recalc_rate,
936 - .determine_rate = jh7100_clk_frac_determine_rate,
937 - .set_rate = jh7100_clk_frac_set_rate,
938 - .debug_init = jh7100_clk_debug_init,
939 +static const struct clk_ops jh71x0_clk_fdiv_ops = {
940 + .recalc_rate = jh71x0_clk_frac_recalc_rate,
941 + .determine_rate = jh71x0_clk_frac_determine_rate,
942 + .set_rate = jh71x0_clk_frac_set_rate,
943 + .debug_init = jh71x0_clk_debug_init,
944 };
945
946 -static const struct clk_ops jh7100_clk_gdiv_ops = {
947 - .enable = jh7100_clk_enable,
948 - .disable = jh7100_clk_disable,
949 - .is_enabled = jh7100_clk_is_enabled,
950 - .recalc_rate = jh7100_clk_recalc_rate,
951 - .determine_rate = jh7100_clk_determine_rate,
952 - .set_rate = jh7100_clk_set_rate,
953 - .debug_init = jh7100_clk_debug_init,
954 +static const struct clk_ops jh71x0_clk_gdiv_ops = {
955 + .enable = jh71x0_clk_enable,
956 + .disable = jh71x0_clk_disable,
957 + .is_enabled = jh71x0_clk_is_enabled,
958 + .recalc_rate = jh71x0_clk_recalc_rate,
959 + .determine_rate = jh71x0_clk_determine_rate,
960 + .set_rate = jh71x0_clk_set_rate,
961 + .debug_init = jh71x0_clk_debug_init,
962 };
963
964 -static const struct clk_ops jh7100_clk_mux_ops = {
965 - .determine_rate = jh7100_clk_mux_determine_rate,
966 - .set_parent = jh7100_clk_set_parent,
967 - .get_parent = jh7100_clk_get_parent,
968 - .debug_init = jh7100_clk_debug_init,
969 +static const struct clk_ops jh71x0_clk_mux_ops = {
970 + .determine_rate = jh71x0_clk_mux_determine_rate,
971 + .set_parent = jh71x0_clk_set_parent,
972 + .get_parent = jh71x0_clk_get_parent,
973 + .debug_init = jh71x0_clk_debug_init,
974 };
975
976 -static const struct clk_ops jh7100_clk_gmux_ops = {
977 - .enable = jh7100_clk_enable,
978 - .disable = jh7100_clk_disable,
979 - .is_enabled = jh7100_clk_is_enabled,
980 - .determine_rate = jh7100_clk_mux_determine_rate,
981 - .set_parent = jh7100_clk_set_parent,
982 - .get_parent = jh7100_clk_get_parent,
983 - .debug_init = jh7100_clk_debug_init,
984 +static const struct clk_ops jh71x0_clk_gmux_ops = {
985 + .enable = jh71x0_clk_enable,
986 + .disable = jh71x0_clk_disable,
987 + .is_enabled = jh71x0_clk_is_enabled,
988 + .determine_rate = jh71x0_clk_mux_determine_rate,
989 + .set_parent = jh71x0_clk_set_parent,
990 + .get_parent = jh71x0_clk_get_parent,
991 + .debug_init = jh71x0_clk_debug_init,
992 };
993
994 -static const struct clk_ops jh7100_clk_mdiv_ops = {
995 - .recalc_rate = jh7100_clk_recalc_rate,
996 - .determine_rate = jh7100_clk_determine_rate,
997 - .get_parent = jh7100_clk_get_parent,
998 - .set_parent = jh7100_clk_set_parent,
999 - .set_rate = jh7100_clk_set_rate,
1000 - .debug_init = jh7100_clk_debug_init,
1001 +static const struct clk_ops jh71x0_clk_mdiv_ops = {
1002 + .recalc_rate = jh71x0_clk_recalc_rate,
1003 + .determine_rate = jh71x0_clk_determine_rate,
1004 + .get_parent = jh71x0_clk_get_parent,
1005 + .set_parent = jh71x0_clk_set_parent,
1006 + .set_rate = jh71x0_clk_set_rate,
1007 + .debug_init = jh71x0_clk_debug_init,
1008 };
1009
1010 -static const struct clk_ops jh7100_clk_gmd_ops = {
1011 - .enable = jh7100_clk_enable,
1012 - .disable = jh7100_clk_disable,
1013 - .is_enabled = jh7100_clk_is_enabled,
1014 - .recalc_rate = jh7100_clk_recalc_rate,
1015 - .determine_rate = jh7100_clk_determine_rate,
1016 - .get_parent = jh7100_clk_get_parent,
1017 - .set_parent = jh7100_clk_set_parent,
1018 - .set_rate = jh7100_clk_set_rate,
1019 - .debug_init = jh7100_clk_debug_init,
1020 +static const struct clk_ops jh71x0_clk_gmd_ops = {
1021 + .enable = jh71x0_clk_enable,
1022 + .disable = jh71x0_clk_disable,
1023 + .is_enabled = jh71x0_clk_is_enabled,
1024 + .recalc_rate = jh71x0_clk_recalc_rate,
1025 + .determine_rate = jh71x0_clk_determine_rate,
1026 + .get_parent = jh71x0_clk_get_parent,
1027 + .set_parent = jh71x0_clk_set_parent,
1028 + .set_rate = jh71x0_clk_set_rate,
1029 + .debug_init = jh71x0_clk_debug_init,
1030 };
1031
1032 -static const struct clk_ops jh7100_clk_inv_ops = {
1033 - .get_phase = jh7100_clk_get_phase,
1034 - .set_phase = jh7100_clk_set_phase,
1035 - .debug_init = jh7100_clk_debug_init,
1036 +static const struct clk_ops jh71x0_clk_inv_ops = {
1037 + .get_phase = jh71x0_clk_get_phase,
1038 + .set_phase = jh71x0_clk_set_phase,
1039 + .debug_init = jh71x0_clk_debug_init,
1040 };
1041
1042 -const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
1043 +const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
1044 {
1045 - if (max & JH7100_CLK_DIV_MASK) {
1046 - if (max & JH7100_CLK_MUX_MASK) {
1047 - if (max & JH7100_CLK_ENABLE)
1048 - return &jh7100_clk_gmd_ops;
1049 - return &jh7100_clk_mdiv_ops;
1050 + if (max & JH71X0_CLK_DIV_MASK) {
1051 + if (max & JH71X0_CLK_MUX_MASK) {
1052 + if (max & JH71X0_CLK_ENABLE)
1053 + return &jh71x0_clk_gmd_ops;
1054 + return &jh71x0_clk_mdiv_ops;
1055 }
1056 - if (max & JH7100_CLK_ENABLE)
1057 - return &jh7100_clk_gdiv_ops;
1058 - if (max == JH7100_CLK_FRAC_MAX)
1059 - return &jh7100_clk_fdiv_ops;
1060 - return &jh7100_clk_div_ops;
1061 + if (max & JH71X0_CLK_ENABLE)
1062 + return &jh71x0_clk_gdiv_ops;
1063 + if (max == JH71X0_CLK_FRAC_MAX)
1064 + return &jh71x0_clk_fdiv_ops;
1065 + return &jh71x0_clk_div_ops;
1066 }
1067
1068 - if (max & JH7100_CLK_MUX_MASK) {
1069 - if (max & JH7100_CLK_ENABLE)
1070 - return &jh7100_clk_gmux_ops;
1071 - return &jh7100_clk_mux_ops;
1072 + if (max & JH71X0_CLK_MUX_MASK) {
1073 + if (max & JH71X0_CLK_ENABLE)
1074 + return &jh71x0_clk_gmux_ops;
1075 + return &jh71x0_clk_mux_ops;
1076 }
1077
1078 - if (max & JH7100_CLK_ENABLE)
1079 - return &jh7100_clk_gate_ops;
1080 + if (max & JH71X0_CLK_ENABLE)
1081 + return &jh71x0_clk_gate_ops;
1082
1083 - return &jh7100_clk_inv_ops;
1084 + return &jh71x0_clk_inv_ops;
1085 }
1086 -EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
1087 +EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
1088 --- a/drivers/clk/starfive/clk-starfive-jh71x0.h
1089 +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
1090 @@ -1,6 +1,6 @@
1091 /* SPDX-License-Identifier: GPL-2.0 */
1092 -#ifndef __CLK_STARFIVE_JH7100_H
1093 -#define __CLK_STARFIVE_JH7100_H
1094 +#ifndef __CLK_STARFIVE_JH71X0_H
1095 +#define __CLK_STARFIVE_JH71X0_H
1096
1097 #include <linux/bits.h>
1098 #include <linux/clk-provider.h>
1099 @@ -8,107 +8,116 @@
1100 #include <linux/spinlock.h>
1101
1102 /* register fields */
1103 -#define JH7100_CLK_ENABLE BIT(31)
1104 -#define JH7100_CLK_INVERT BIT(30)
1105 -#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
1106 -#define JH7100_CLK_MUX_SHIFT 24
1107 -#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
1108 -#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
1109 -#define JH7100_CLK_FRAC_SHIFT 8
1110 -#define JH7100_CLK_INT_MASK GENMASK(7, 0)
1111 +#define JH71X0_CLK_ENABLE BIT(31)
1112 +#define JH71X0_CLK_INVERT BIT(30)
1113 +#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
1114 +#define JH71X0_CLK_MUX_SHIFT 24
1115 +#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
1116 +#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
1117 +#define JH71X0_CLK_FRAC_SHIFT 8
1118 +#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
1119
1120 /* fractional divider min/max */
1121 -#define JH7100_CLK_FRAC_MIN 100UL
1122 -#define JH7100_CLK_FRAC_MAX 25599UL
1123 +#define JH71X0_CLK_FRAC_MIN 100UL
1124 +#define JH71X0_CLK_FRAC_MAX 25599UL
1125
1126 /* clock data */
1127 -struct jh7100_clk_data {
1128 +struct jh71x0_clk_data {
1129 const char *name;
1130 unsigned long flags;
1131 u32 max;
1132 u8 parents[4];
1133 };
1134
1135 -#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
1136 +#define JH71X0_GATE(_idx, _name, _flags, _parent) \
1137 +[_idx] = { \
1138 .name = _name, \
1139 .flags = CLK_SET_RATE_PARENT | (_flags), \
1140 - .max = JH7100_CLK_ENABLE, \
1141 + .max = JH71X0_CLK_ENABLE, \
1142 .parents = { [0] = _parent }, \
1143 }
1144
1145 -#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
1146 +#define JH71X0__DIV(_idx, _name, _max, _parent) \
1147 +[_idx] = { \
1148 .name = _name, \
1149 .flags = 0, \
1150 .max = _max, \
1151 .parents = { [0] = _parent }, \
1152 }
1153
1154 -#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
1155 +#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
1156 +[_idx] = { \
1157 .name = _name, \
1158 .flags = _flags, \
1159 - .max = JH7100_CLK_ENABLE | (_max), \
1160 + .max = JH71X0_CLK_ENABLE | (_max), \
1161 .parents = { [0] = _parent }, \
1162 }
1163
1164 -#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
1165 +#define JH71X0_FDIV(_idx, _name, _parent) \
1166 +[_idx] = { \
1167 .name = _name, \
1168 .flags = 0, \
1169 - .max = JH7100_CLK_FRAC_MAX, \
1170 + .max = JH71X0_CLK_FRAC_MAX, \
1171 .parents = { [0] = _parent }, \
1172 }
1173
1174 -#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
1175 +#define JH71X0__MUX(_idx, _name, _nparents, ...) \
1176 +[_idx] = { \
1177 .name = _name, \
1178 .flags = 0, \
1179 - .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
1180 + .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
1181 .parents = { __VA_ARGS__ }, \
1182 }
1183
1184 -#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
1185 +#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
1186 +[_idx] = { \
1187 .name = _name, \
1188 .flags = _flags, \
1189 - .max = JH7100_CLK_ENABLE | \
1190 - (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
1191 + .max = JH71X0_CLK_ENABLE | \
1192 + (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
1193 .parents = { __VA_ARGS__ }, \
1194 }
1195
1196 -#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
1197 +#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
1198 +[_idx] = { \
1199 .name = _name, \
1200 .flags = 0, \
1201 - .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
1202 + .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
1203 .parents = { __VA_ARGS__ }, \
1204 }
1205
1206 -#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
1207 +#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
1208 +[_idx] = { \
1209 .name = _name, \
1210 .flags = _flags, \
1211 - .max = JH7100_CLK_ENABLE | \
1212 - (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
1213 + .max = JH71X0_CLK_ENABLE | \
1214 + (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
1215 .parents = { __VA_ARGS__ }, \
1216 }
1217
1218 -#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
1219 +#define JH71X0__INV(_idx, _name, _parent) \
1220 +[_idx] = { \
1221 .name = _name, \
1222 .flags = CLK_SET_RATE_PARENT, \
1223 - .max = JH7100_CLK_INVERT, \
1224 + .max = JH71X0_CLK_INVERT, \
1225 .parents = { [0] = _parent }, \
1226 }
1227
1228 -struct jh7100_clk {
1229 +struct jh71x0_clk {
1230 struct clk_hw hw;
1231 unsigned int idx;
1232 unsigned int max_div;
1233 };
1234
1235 -struct jh7100_clk_priv {
1236 +struct jh71x0_clk_priv {
1237 /* protect clk enable and set rate/parent from happening at the same time */
1238 spinlock_t rmw_lock;
1239 struct device *dev;
1240 void __iomem *base;
1241 struct clk_hw *pll[3];
1242 - struct jh7100_clk reg[];
1243 + struct jh71x0_clk reg[];
1244 };
1245
1246 -const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
1247 +const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
1248
1249 #endif
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