target/linux/generic/backport-6.1/790-32-v6.9-net-dsa-mt7530-simplify-mt7530_pad_clk_setup.patch

   1 From 7199c736aa8cd9c69ae681a9c733408372c2ce76 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Tue, 6 Feb 2024 01:08:04 +0300
   4 Subject: [PATCH 32/48] net: dsa: mt7530: simplify mt7530_pad_clk_setup()
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 This code is from before this driver was converted to phylink API. Phylink
  10 deals with the unsupported interface cases before mt7530_pad_clk_setup() is
  11 run. Therefore, the default case would never run. However, it must be
  12 defined nonetheless to handle all the remaining enumeration values, the
  13 phy-modes.
  14
  15 Switch to if statement for RGMII and return which simplifies the code and
  16 saves an indent.
  17
  18 Set P6_INTF_MODE, which is the three least significant bits of the
  19 MT7530_P6ECR register, to 0 for RGMII even though it will already be 0
  20 after reset. This is to keep supporting dynamic reconfiguration of the port
  21 in the case the interface changes from TRGMII to RGMII.
  22
  23 Disable the TRGMII clocks for all cases. They will be enabled if TRGMII is
  24 being used.
  25
  26 Read XTAL after checking for RGMII as it's only needed for the TRGMII
  27 interface mode.
  28
  29 Reviewed-by: Daniel Golle <daniel@makrotopia.org>
  30 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  31 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  32 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  33 Link: https://lore.kernel.org/r/20240206-for-netnext-mt7530-improvements-2-v5-3-d7d92a185cb1@arinc9.com
  34 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  35 ---
  36  drivers/net/dsa/mt7530.c | 91 ++++++++++++++++++----------------------
  37  1 file changed, 40 insertions(+), 51 deletions(-)
  38
  39 --- a/drivers/net/dsa/mt7530.c
  40 +++ b/drivers/net/dsa/mt7530.c
  41 @@ -404,65 +404,54 @@ static int
  42  mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
  43  {
  44         struct mt7530_priv *priv = ds->priv;
  45 -       u32 ncpo1, ssc_delta, trgint, xtal;
  46 +       u32 ncpo1, ssc_delta, xtal;
  47
  48 -       xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
  49 +       /* Disable the MT7530 TRGMII clocks */
  50 +       core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
  51
  52 -       switch (interface) {
  53 -       case PHY_INTERFACE_MODE_RGMII:
  54 -               trgint = 0;
  55 -               break;
  56 -       case PHY_INTERFACE_MODE_TRGMII:
  57 -               trgint = 1;
  58 -               if (xtal == HWTRAP_XTAL_25MHZ)
  59 -                       ssc_delta = 0x57;
  60 -               else
  61 -                       ssc_delta = 0x87;
  62 -               if (priv->id == ID_MT7621) {
  63 -                       /* PLL frequency: 125MHz: 1.0GBit */
  64 -                       if (xtal == HWTRAP_XTAL_40MHZ)
  65 -                               ncpo1 = 0x0640;
  66 -                       if (xtal == HWTRAP_XTAL_25MHZ)
  67 -                               ncpo1 = 0x0a00;
  68 -               } else { /* PLL frequency: 250MHz: 2.0Gbit */
  69 -                       if (xtal == HWTRAP_XTAL_40MHZ)
  70 -                               ncpo1 = 0x0c80;
  71 -                       if (xtal == HWTRAP_XTAL_25MHZ)
  72 -                               ncpo1 = 0x1400;
  73 -               }
  74 -               break;
  75 -       default:
  76 -               dev_err(priv->dev, "xMII interface %d not supported\n",
  77 -                       interface);
  78 -               return -EINVAL;
  79 +       if (interface == PHY_INTERFACE_MODE_RGMII) {
  80 +               mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
  81 +                          P6_INTF_MODE(0));
  82 +               return 0;
  83         }
  84
  85 -       mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
  86 -                  P6_INTF_MODE(trgint));
  87 +       mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
  88
  89 -       if (trgint) {
  90 -               /* Disable the MT7530 TRGMII clocks */
  91 -               core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
  92 -
  93 -               /* Setup the MT7530 TRGMII Tx Clock */
  94 -               core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
  95 -               core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
  96 -               core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
  97 -               core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
  98 -               core_write(priv, CORE_PLL_GROUP4,
  99 -                          RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
 100 -                          RG_SYSPLL_BIAS_LPF_EN);
 101 -               core_write(priv, CORE_PLL_GROUP2,
 102 -                          RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
 103 -                          RG_SYSPLL_POSDIV(1));
 104 -               core_write(priv, CORE_PLL_GROUP7,
 105 -                          RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
 106 -                          RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
 107 +       xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
 108
 109 -               /* Enable the MT7530 TRGMII clocks */
 110 -               core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
 111 +       if (xtal == HWTRAP_XTAL_25MHZ)
 112 +               ssc_delta = 0x57;
 113 +       else
 114 +               ssc_delta = 0x87;
 115 +
 116 +       if (priv->id == ID_MT7621) {
 117 +               /* PLL frequency: 125MHz: 1.0GBit */
 118 +               if (xtal == HWTRAP_XTAL_40MHZ)
 119 +                       ncpo1 = 0x0640;
 120 +               if (xtal == HWTRAP_XTAL_25MHZ)
 121 +                       ncpo1 = 0x0a00;
 122 +       } else { /* PLL frequency: 250MHz: 2.0Gbit */
 123 +               if (xtal == HWTRAP_XTAL_40MHZ)
 124 +                       ncpo1 = 0x0c80;
 125 +               if (xtal == HWTRAP_XTAL_25MHZ)
 126 +                       ncpo1 = 0x1400;
 127         }
 128
 129 +       /* Setup the MT7530 TRGMII Tx Clock */
 130 +       core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
 131 +       core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
 132 +       core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
 133 +       core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
 134 +       core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN |
 135 +                  RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN);
 136 +       core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL |
 137 +                  RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1));
 138 +       core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG |
 139 +                  RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
 140 +
 141 +       /* Enable the MT7530 TRGMII clocks */
 142 +       core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN);
 143 +
 144         return 0;
 145  }
 146